CS5505-AS datasheet(18/40 Pages) CIRRUS

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Analog Input Impedance Considerations

The analog input of the CS5505/6/7/8 can be

modeled as illustrated in Figure 8 (the model ig-

nores the multiplexer switch resistance).

Capacitors (15 pF each) are used to dynamically

sample each of the inputs (AIN+ and AIN-).

Every half XIN cycle the switch alternately con-

nects the capacitor to the output of the buffer

and then directly to the AIN pin. Whenever the

sample capacitor is switched from the output of

the buffer to the AIN pin, a small packet of

charge (a dynamic demand of current) is re-

quired from the input source to settle the voltage

of the sample capacitor to its final value. The

voltage on the output of the buffer may differ up

to 100 mV from the actual input voltage due to

the offset voltage of the buffer. Timing allows

one half of a XIN clock cycle for the voltage on

the sample capacitor to settle to its final value.

The equation which defines the settling time is:

= Vmax e

−t

⁄RC

Where Ve is the final settled value, Vmax is the

maximum error voltage value of the input signal,

R is the value of the input source resistance, C is

the 15 pF sample capacitor plus the value of any

stray or additional capacitance at the input pin.

The value of t is equal to 1/(2XIN).

Vmax occurs the instant the sample capacitor is

switched from the buffer output to the AIN pin.

Prior to switching, AIN has an error estimated as

being less than or equal to Ve. Vmax is equal to

the prior error (Ve) plus the additional error

from the buffer offset. The estimate for Vmax is:

Vmax

= Ve + 100mV

15pF

(15pF + CEXT )

Where CEXT is the combination of any external

or stray capacitance.

From the settling time equation, an equation for

the maximum acceptable source resistance is de-

rived.

Rsmax

−1

2XIN

(15pF + CEXT ) ln 







15pF

(100mv)

(15pF + CEXT )









This equation assumes that the offset voltage of

the buffer is 100 mV, which is the worst case.

The value of Ve is the maximum error voltage

which is acceptable.

For a maximum error voltage (Ve) of 10

µV in

the CS5505 (1/4LSB at 16-bits) and 600 nV in

the CS5506 (1/4LSB at 20-bits), the above equa-

tion indicates that when operating from a

32.768 kHz XIN, source resistances up to

110 k

Ω in the CS5505 or 84 kΩ in the CS5506

are acceptable in the absence of external capaci-

tance (CEXT = 0). If higher input source

resistances are desired the master clock rate can

be reduced to yield a longer settling time.

The VREF+ and VREF- inputs have nearly the

same structure as the AIN+ and AIN- inputs.

Therefore, the discussion on analog input imped-

ance applies to the voltage reference inputs as

well.

15 pF

Vos < 100 mV

Internal

Bias

Voltage

15 pF

AIN+

AIN-

CS5505/6/7/8

Figure 8. Analog Input Model

CS5505/6/7/8

DS59F4

CS5505/6/7/8

DS59F5

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