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PIFE32251B-R68MS 数据表(PDF) 63 Page - Texas Instruments |
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PIFE32251B-R68MS 数据表(HTML) 63 Page - Texas Instruments |
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63 / 157 page  ENABLE ENVRx VRx VOUT POWERGOOD FB VOUT FBVRxP PGVRx Lout Cout 0.90*VREF Vout (Enable) time PGVRx (Powergood) 30 us deglitch ENVRx PWRGD threshold 0 0 ENVRx FBVRxP (Vout) 1.10*VREF PGVRx Programmable Discharge Resistance 0 VREF Copyright © 2016, Texas Instruments Incorporated 63 TPS650830 www.ti.com SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 Submit Documentation Feedback Product Folder Links: TPS650830 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated 6.3.11 Enable and Powergood of VRs The VRs are enabled by the ENVRx pins. The powergood is output on the PGVRx pins. The powergood pins can be defined as open-drain or push-pull output, depending on the function in order to allow "ANDing" or to reduce external components and quiescent current. there is a 30-µs deglitch on both edges of the powergood comparator outputs. A status register monitors the powergood outputs, and the powergood tree monitors the powergood for proper sequence and protection. The powergood signals can be masked by a register. Figure 6-12. Enable and Powergood of VRs |
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