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PIFE32251B-R68MS 数据表(PDF) 78 Page - Texas Instruments |
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PIFE32251B-R68MS 数据表(HTML) 78 Page - Texas Instruments |
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78 / 157 page  78 TPS650830 SLVSCF4A – DECEMBER 2014 – REVISED JULY 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS650830 Detailed Description Copyright © 2014–2016, Texas Instruments Incorporated 6.6.1.3 IRQLVL1 Register (address = 0x02) [reset = 00000000] Figure 6-25. IRQLVL1 Register Format B7 B6 B5 B4 B3 B2 B1 B0 RESET RESERVED2 PMU RESERVED1[1 ] RESERVED1[0 ] PWRSRC RESERVED PWRBTN 0 0 0 0 0 0 0 0 RW R RW R R RW R RW LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-6. IRQLVL1 Register Field Descriptions Bit Field Type Reset Description 7 RESET R 0 RESET interrupt 0: Not asserted 1: Asserted 6 RESERVED2 R 0 5 PMU R 0 Power monitor interrupt 0: Not asserted 1: Asserted 4:3 RESERVED1[1:0] R 00 2 PWRSRC R 0 Power source interrupt 0: Not asserted 1: Asserted 1 RESERVED R 0 0 PWRBTN RW 0 Power button interrupt 0: Not asserted 1: Asserted, write '1' to clear |
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