M28W320ECT datasheet(40/53 Pages) STMICROELECTRONICS

40 / 53 page

M28W320ECT, M28W320ECB

40/53

Table 30. Primary Algorithm-Specific Extended Query Table

Note: 1. See Table 27, offset 15 for P pointer definition.

Offset

P = 35h (1)

Data

Description

Value

(P+0)h = 35h

0050h

Primary Algorithm extended Query table unique ASCII string “PRI”

"P"

(P+1)h = 36h

0052h

"R"

(P+2)h = 37h

0049h

"I"

(P+3)h = 38h

0031h

Major version number, ASCII

"1"

(P+4)h = 39h

0030h

Minor version number, ASCII

"0"

(P+5)h = 3Ah

0066h

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

Chip Erase supported

(1 = Yes, 0 = No)

bit 1

Suspend Erase supported

(1 = Yes, 0 = No)

bit 2

Suspend Program supported

(1 = Yes, 0 = No)

bit 3

Legacy Lock/Unlock supported

(1 = Yes, 0 = No)

bit 4

Queued Erase supported

(1 = Yes, 0 = No)

bit 5

Instant individual block locking supported (1 = Yes, 0 = No)

bit 6

Protection bits supported

(1 = Yes, 0 = No)

bit 7

Page mode read supported

(1 = Yes, 0 = No)

bit 8

Synchronous read supported

(1 = Yes, 0 = No)

bit 31 to 9

Reserved; undefined bits are ‘0’

Yes

(P+6)h = 3Bh

0000h

(P+7)h = 3Ch

0000h

(P+8)h = 3Dh

0000h

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0

Program supported after Erase Suspend (1 = Yes, 0 = No)

bit 7 to 1

Reserved; undefined bits are ‘0’

Yes

(P+A)h = 3Fh

0003h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0

Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No)

bit 1

Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2

Reserved for future use; undefined bits are ‘0’

Yes

(P+B)h = 40h

0000h

(P+C)h = 41h

0030h

VDD Logic Supply Optimum Program/Erase voltage (highest performance)

bit 7 to 4

HEX value in volts

bit 3 to 0

BCD value in 100 mV

(P+D)h = 42h

00C0h

VPP Supply Optimum Program/Erase voltage

bit 7 to 4

HEX value in volts

bit 3 to 0

BCD value in 100 mV

12V

(P+E)h = 43h

0001h

Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h

0080h

Protection Field 1: Protection Description

This field describes user-available. One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection register Lock byte, the section’s first byte.

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7

Lock/bytes JEDEC-plane physical low address

bit 8 to 15

Lock/bytes JEDEC-plane physical high address

bit 16 to 23

"n" such that 2n = factory pre-programmed bytes

bit 24 to 31

"n" such that 2n = user programmable bytes

80h

(P+10)h = 45h

0000h

00h

(P+11)h = 46h

0003h

8 Byte

(P+12)h = 47h

0003h

8 Byte

(P+13)h = 48h

Reserved

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