AS4C2M32SA-6TCN datasheet(26/54 Pages) ALSC

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Figure 23. Self Refresh Entry & Exit Cycle

Don’t Care

CLK

Self Refresh

Entry

Auto Refresh

tIS

CKE

Hi-Z

Self Refresh Exit

RAS#

CAS#

BA0,1

A0-A9

WE#

*Note 1

*Note 5

tXSR

tPDE

*Note 7

DQM

Hi-Z

*Note 9

*Note 8

tIH

*Note 6

tIS

CS#

T0 T1 T2 T3 T4 T5

T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19

*Note 3, 4

*Note 2

Note:

To Enter SelfRefresh Mode

1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.

3. The device remains in SelfRefresh mode as long as CKE stays "low".

4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.

To Exit SelfRefresh Mode

5. System clock restart and be stable before returning CKE high.

6. Enable CKE and CKE should be set high for valid setup time and hold time.

7. CS# starts from high.

8. Minimum tXSR is required after CKE going high to complete SelfRefresh exit.

9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the

system uses burst refresh.

AS4C2M32SA-6TIN

AS4C2M32SA-6TCN

AS4C2M32SA-7TCN

Confidential

-26/54-

Rev.1.0 Sep. 2015

AS4C2M32SA-6TCN 数据表(PDF) 26 Page - Alliance Semiconductor Corporation

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