PC87382 datasheet(12/72 Pages) NSC

12 / 72 page

1.0 Signal/Pin Connection and Description (Continued)

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Revision1.2

1.3.7

Power and Ground

1.3.8

Strap Configuration

1.3.9

Test and Miscellaneous

Signal

Pin(s)

I/O

Buffer Type

Description

VDD

35, 24, 8

PWR

Main 3.3V Power Supply.

VSS

34, 23, 9

GND

Ground.

Signal

Pin(s)

I/O

Buffer Type

Description

BADDR

INTS

Base Address. Sampled at VDD Power-Up reset to determine the base

address of the conﬁguration Index-Data register pair.

– No pull-down resistor (default)

- the Index-Data pair at

164Eh-164Fh.

–10K

Ω1 external pull-down resistor - the Index-Data pair at 2Eh-2Fh1.

The external pull-down resistor must be connected to VSS.

1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recommended

for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 K

Ω. If, however, a TTL

transceiver device is used, the value of the external pull-down resistor must be 470

Ω, and since the Serial Port

pins are not able to drive this load, the external pull-down resistor must disconnect tEPLV after VDD power-up

(see Section 8.4.5 on page 66).

TRIS

INTS

TRI-STATE Device. Sampled at VDD Power-Up to force the device to

ﬂoat all its output and I/O pins.

– No pull-down resistor (default)

- normal pin operation

–10K

Ω1 external pull-down resistor - ﬂoating device pins

The external pull-down resistor must be connected to VSS.

When TRIS is set to 0 (by an external pull-down resistor), TEST must be

1 (i.e., left unconnected).

TEST

INTS

XOR Tree Test Mode. Sampled at VDD Power-Up to force the device

pins into a XOR tree conﬁguration.

– No pull-down resistor (default)

- normal device operation

–10K

Ω1 external pull-down resistor - pins conﬁgured as XOR tree.

The external pull-down resistor must be connected to VSS.

When TEST is set to 0 (by an external pull-down resistor), TRIS must be

1 (i.e., left unconnected).

Signal

Pin(s)

I/O

Buffer Type

Description

XOR_OUT

O3/6

XOR Tree Output. All the device pins (except ground and power pins)

are internally connected in a XOR tree structure.

VCORF

I/O

On-Chip Core Power Converter Filter. Powers the core logic of all the

device modules. An external 0.1

µF ceramic ﬁlter capacitor must be

connected between this pin and VSS.

PC87382 数据表(PDF) 12 Page - National Semiconductor (TI)

PC87382 数据表(HTML) 12 Page - National Semiconductor (TI)

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PC87382 数据表(PDF) 12 Page - National Semiconductor (TI)

PC87382 数据表(HTML) 12 Page - National Semiconductor (TI)

Html Pages

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链接网址

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