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PC87382 数据表(PDF) 2 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 PC87382
功能描述  LPC-to-LPC Switch for Docking Stations, with Fast Infrared Port, Serial Port and GPIOs
PDF  72 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

PC87382 数据表(HTML) 2 Page - National Semiconductor (TI)

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Revision 1.2
Features
LPC System Interface
— 8-bit I/O cycles
— CLKRUN support
— Implements PCI mobile design guide recommenda-
tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998)
LPC-to-LPC Switch
— Hot plugability
— CLKRUN support
— The connection is controlled by software
— Low switch resistance and propagation delay
— Programmable Clock to Reset Delay
PC2001 and ACPI Compliant
— PnP Configuration Register structure
— Flexible resource allocation for all logical devices
❏ Relocatable base address
❏ 15 IRQ routing options
❏ Two optional 8-bit DMA channels (where applica-
ble) selected from four possible DMA channels
Clock Sources
— 14.318 MHz or 48 MHz clock input
— LPC clock, up to 33 MHz
— 14.318 MHz or 48 MHz clock output to the docking
station
Power Supply
— 3.3V supply operation
— All pins are 5V tolerant, except LPC bus pins
— All pins are back-drive protected, except LPC bus pins
Eight General-Purpose I/O (GPIO) Ports
— Support assert IRQ
— Programmable drive type for each output pin (open-
drain, push-pull or output disable)
— Programmable option for internal pull-up resistor on
each input pin
— Output lock option
— Input debounce mechanism
Serial Port (SP1)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
Fast Infrared Port (FIR)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— FIR IrDA 1.1 compliant
— HP-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control supports RC-5, RC-6,
NEC, RCA and RECS 80
— DMA support: 1 or 2 channels
Strap Configuration
— Base Address (BADDR) strap to determine the base
address of the Index-Data register pair
— Strap Inputs to select testability mode
Testability
— XOR Tree
— TRI-STATE device pins
Internal Block Diagram
Infrared
Interface
Bus
Interface
LPC Interface
I/O
Serial Port 1
Serial
Interface
FIR
GPIO Ports
Ports
Docking
LPC Switch
Docking LPC
Interface
14.31818 MHz
Clock
Generator
48 MHz



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