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STV82X6 数据表(PDF) 36 Page - STMicroelectronics

部件名 STV82X6
功能描述  Multistandard TV Audio Processor and Digital Sound Demodulator
PDF  95 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STV82X6 数据表(HTML) 36 Page - STMicroelectronics

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Register List
STV82x6
36/95
CTRL
Hardware Interface Control Register
Description
Provides all hardware controls to drive external components (SAW Filter, Audio Switches) and
additional Audio Decoder (Dolby Pro Logic) via register I2S including the Master and Quartz Clocks.
Bit Name
Reset
Function
Bit7
0
Reserved.
SCLPD_OFF
SCL Pulling-down System Disable
0: System is enabled
1: System is disabled
AUTO_OFF
0
Automatic Standard Recognition System Disable
0: System is enabled
1: System is disabled
Bits[4:3]
00
Reserved.
SOFT_LRESTART1
0
Softreset (active high) of Channel 1 detectors only.
SOFT_LRESTART2
0
Softreset (active high) of Channel 2 detectors only.
SOFTRST
0
General softreset (active high) to reset all hardware registers except for I²C data.
Address (hex): 03h
Type: R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
BUS_EXPAND[1:0]
I2S_EN
SDI_EN
0
MCK_EN
SYSCK_EN
Bit Name
Reset
Function
Bit 7
0
Reserved.
BUS_EXPAND[1:0]
00
Static control by I²C of hardware pins BUS1 and BUS0.
I2S_EN
0
When 1, the I²S hardware pin is enabled (SCK, WS, SDO)
SDI_EN
0
When 1, the SDI input pin is enabled (switch with ST output). Must be used when I²S mode is
selected.
Bit 2
0
Reserved.
MCK_EN
0
Master Clock Enable
Enables the master clock output (256.fs) to interface by I²S with the Dolby Pro Logic Decoder.
0: Disabled.
1: Enabled
SYSCK-EN
0
System Clock Enable
Enables the system clock output to provide the quartz clock required to interface with the Dolby
Pro Logic Decoder.
0: Disabled.
1: Enabled



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