ADE3050SX datasheet(19/88 Pages) STMICROELECTRONICS

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ADE3XXX

Line Lock PLL Block

2.4

Line Lock PLL Block

The line lock PLL recovers a sample clock from an incoming hsync source. The response

characteristics of the line lock PLL are adjustable for optimimum response time and jitter filtering.

The phase of the sample clock is digitally adjustable by steps of 289 ps (with a 27-MHz crystal). The

I2C interface of the line lock PLL is in the LLK_CTRL clock domain which must be active for

programming.

The PLL loop filter has three ranges with independent filter parameters. When the phase detector

error remains below a programmable threshold for a programmable number of input lines, the loop

filter coefficients change. Any phase detector error above the programmed threshold reverts the

filter to the appropriate level in one line. The operation is represented in Figure 3.

The digital loop filter is controlled by three parameters: MFACTOR, A and B. M_FACTOR is the

desired number of clocks per input line. The A and B parameters control the response of the 2nd

order digital filter. A and B are composed of a linear and exponential component designated by the

L and E suffix, respectively. These numbers are related to the classic 2nd order damping and

natural frequency as follows:

Damping = AL x 2

(AE-12) x SQRT(5 x M_FACTOR / (BL x 2BE))

Natural Frequency = SQRT(M_FACTOR x 5 x BL x 2

(BE-34))

Figure 3: Line Lock PLL State Diagram

Table 7: Line Lock PLL Registers (Sheet 1 of 4)

Addr

Mode

Bits

Default

Description

LLK_PLL_CLEAR

0x0800

[7:6]

Reserved

R/W

[5]

0x0

Master Reset

R/W

[4]

0x0

Reset the PLL synthetic sync

R/W

[3]

0x0

Reset PLL offset

R/W

[2]

0x0

Reset PLL accumulator

R/W

[1]

0x0

Reset the low pass filter

R/W

[0]

0x0

Reset the PLL phase error

fast

slow

lock

more than SLOW_LINE_NB

error <= SLOW_TOL for

of lines

error > LOCK_TOL

error <= LOCK_TOL for

more than LOCK_LINE_NB

of lines

error > SLOW_TOL

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