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ADE3050SX 数据表(PDF) 32 Page - STMicroelectronics |
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ADE3050SX 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 88 page ![]() Sync Measurement Block ADE3XXX 32/88 2.9 Sync Measurement Block The Input Sync Measurement Block (SMEAS) continuously detects activity from all video sources. The module can measure the characteristics of the sync signals on any input port. The sync measurement module reports the results of the measurements to the system microcontroller. This portion of the sync measurement is fully synchronous on the crystal clock (XCLK). Another block, the Sync Retiming Block (SRT), handles the asynchronous signal transfer of the incoming sync signals. Input Sync Functions: q Activity detection q Sync management q Measurement Table 13: Sync Measurement Registers (Sheet 1 of 8) Register Name Addr Mode Bits Default Description SMEAS_ACT_CTRL 0x0100 [7:4] 0x0 Reserved R/W [3] 0x0 Enable activity detection in Free-running mode. R/W [2] 0x0 Freeze results in Free-running mode. No meaning in One-shot mode. 0: Do not freeze the results. New result will be available on the next and subsequent toggle of the polling bit. 1: Freeze the current results. The polling bit will still toggle and the block continues to free run; however, results will not be updated. R/W [1] 0x0 activity detection start. In one-shot mode it triggers the start of a measurement and is reset to zero when the measurement is complete. R/W [0] 0x0 activity detection mode control 0: free run 1: one shot SMEAS_ACT_H_SMPTM_L 0x0101 R/W [7:0] 0x0 Sample time value for clock or hsync activity. In units of XCLK_period*256 SMEAS_ACT_H_SMPTM_H 0x0102 R/W [7:0] 0x0 SMEAS_ACT_V_SMPTM_L 0x0103 R/W [7:0] 0x0 Sample time value for vsync activity in units of XCLK_period*256. Note: this number MUST be larger than hsync sample time. SMEAS_ACT_V_SMPTM_H 0x0104 R/W [7:0] 0x0 SMEAS_ACT_H_MINEDGE 0x0105 R/W [7:0] 0x0 Minimum edge count value for clk or hsync activity. SMEAS_ACT_V_MINEDGE 0x0106 R/W [7:0] 0x0 Minimum edge count value for vsync activity. SMEAS_H_TMOT_L 0x0107 R/W [7:0] 0x4000 timeout counter value for clk or horizontal measurement in XCLKs SMEAS_H_TMOT_H 0x0108 R/W [7:0] SMEAS_V_TMOT_L 0x0109 R/W [7:0] 0x1600 timeout counter value for vertical measurement in units of XCLK/256 SMEAS_V_TMOT_H 0x010A R/W [7:0] |
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