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ADE3050SX 数据表(PDF) 22 Page - STMicroelectronics |
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ADE3050SX 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 88 page  Digital Video Input (DVI) ADE3XXX 22/88 2.5 Digital Video Input (DVI) The DVI receiver has the following features: q compatible with all DVI complaint transmitters up to 140 MHz pixel clock q on chip termination adjustable by I2C and/or one (~10X) external reference resistor q HDCP and standby / power down supported q decoder digitally corrects for skew errors of at least ±1 pixel in reference to any other channel q bitstream can be decoded and measured without the presence of horizontal and vertical sync pulses LLK_PLL_UPDATE 0x0840 R [7] In Free-running mode, toggles when status is updated. In one-shot mode, this bit is set when status is ready. [6:2] Reserved R/W [1] 0x0 0: Free-running mode 1: one-shot mode R/W [0] 0x0 update enable LLK_PLL_STATUS 0x0841 [7:4] Reserved R [3] LLK overflow R [2] coarse error = 0 R [1] in slow mode R [0] in lock mode LLK_PLL_PH_ERROR_L 0x0842 R [7:0] phase error LLK_PLL_PH_ERROR_H 0x0843 R [7:0] LSB = approx. 200ps LLK_PLL_PHASE_RATE_0 0x0844 R [7:0] LLK phase rate LLK_PLL_PHASE_RATE_1 0x0845 R [7:0] fOUT = fXTAL x 2 27+NDIV / PHASE_RATE LLK_PLL_PHASE_RATE_2 0x0846 R [7:0] LLK_PLL_PHASE_RATE_3 0x0847 R [7:0] LLK_PLL_PHASE_RATE_I_0 0x0848 R [7:0] integral phase rate LLK_PLL_PHASE_RATE_I_1 0x0849 R [7:0] LLK_PLL_PHASE_RATE_I_2 0x084A R [7:0] LLK_PLL_PHASE_RATE_I_3 0x084B R [7:0] LLK_PLL_STAT_ERROR_MEAN 0x084C R [7:0] Average Phase Error over STAT_LINES phase error LSB is approx. 200ps LLK_PLL_STAT_ERROR_PP_L 0x084D R [7:0] Peak Phase Error over STAT_LINES LLK_PLL_STAT_ERROR_PP_H 0x084E R [7:0] phase error LSB is approx. 200ps LLK_PLL_STAT_ERROR_ABS_L 0x084F R [7:0] sum of absolute phase errors over STAT_LINES phase error LSB is approx. 200ps LLK_PLL_STAT_ERROR_ABS_H 0x0850 R [7:0] LLK_PLL_STAT_ERROR_GTX 0x0851 [7:0] Reserved Table 7: Line Lock PLL Registers (Sheet 4 of 4) Register Name Addr Mode Bits Default Description |
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