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LAYOUT GUIDELINES

Since the device manages control functions and high-current drivers, layout is one of the most important

things to consider when designing such high current applications.

A good layout solution can generate a benefit in lowering power dissipation on the power paths, reducing

radiation and a proper connection between signal and power ground can optimize the performance of the

control loops.

Integrated power drivers reduce components count and interconnections between control functions and

drivers, reducing the board space.

Here below are listed the main points to focus on when starting a new layout and rules are suggested for

a correct implementation.

These are the connections where switching and continuous current flows from the input supply towards

the load. The first priority when placing components has to be reserved to this power section, minimizing

the length of each connection as much as possible.

To minimize noise and voltage spikes (EMI and losses) these interconnections must be a part of a power

plane and anyway realized by wide and thick copper traces.

Figure 15. Power connections and related connections layout guidelines (same for both phases).

The critical components, i.e. the power transistors, must be located as close as possible, together and to

the controller. Considering that the "electrical" components reported in figure are composed by more than

one "physical" component, a ground plane or "star" grounding connection is suggested to minimize effects

due to multiple connections.

Fig. 15a shows the details of the power connections involved and the current loops. The input capacitance

order to eliminate the stray inductance generated by the copper traces. Low ESR and ESL capacitors are

required.

Fig.15b shows some small signal components placement, and how and where to mix signal and power

ground planes. The distance from drivers and mosfet gates should be reduced as much as possible. Prop-

agation delay times as well as for the voltage spikes generated by the distributed inductance along the

copper traces are so minimized.

In fact, the further the mosfet is from the device, the longer is the interconnecting gate trace and as a con-

sequence, the higher are the voltage spikes corresponding to the gate PWM rising and falling signals.

Even if these spikes are clamped by inherent internal diodes, propagation delays, noise and potential

LOAD

HS

LS

HGATEx

PHASEx

LGATEx

PGNDx

L

D

LOAD

HS

LS

BOOTx

PHASEx

VCC

SGND

L

D

a. PCB power and ground planes areas

b. PCB small signal components placement