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OMAP3530ECUS 数据表(PDF) 35 Page - Texas Instruments |
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OMAP3530ECUS 数据表(HTML) 35 Page - Texas Instruments |
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35 / 265 page  OMAP3530, OMAP3525 www.ti.com SPRS507H – FEBRUARY 2008 – REVISED OCTOBER 2013 Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued) BALL BALL TOP PIN NAME MODE [4] TYPE [5] BALL BALL RESET REL. POWER [9] HYS [10] BUFFER PULLUP IO CELL [13] BOTTOM [1] [2] [3] RESET RESET REL. MODE [8] STRENG TH /DOWN STATE [6] STATE [7] (mA) [11] TYPE [12] safe_mode 7 AH19 NA gpio_113 4 I L L 7 vdds Yes NA PU/PD LVCMOS safe_mode 7 AG18 NA gpio_114 4 I L L 7 vdds Yes NA PU/PD LVCMOS safe_mode 7 AH18 NA gpio_115 4 I L L 7 vdds Yes NA PU/PD LVCMOS safe_mode 7 P21 NA mcbsp2_fsx 0 IO L L 7 vdds Yes 4 (3) PU/ PD LVCMOS gpio_116 4 IO safe_mode 7 N21 NA mcbsp2_ 0 IO L L 7 vdds Yes 4 (3) PU/ PD LVCMOS clkx gpio_117 4 IO safe_mode 7 R21 NA mcbsp2_dr 0 I L L 7 vdds Yes 4 (3) PU/ PD LVCMOS gpio_118 4 IO safe_mode 7 M21 NA mcbsp2_dx 0 IO L L 7 vdds Yes 4 (4) PU/ PD LVCMOS gpio_119 4 IO safe_mode 7 N28 NA mmc1_clk 0 O L L 7 vdds_mmc1 Yes 8 PU/ PD (5) LVCMOS gpio_120 4 IO safe_mode 7 M27 NA mmc1_cmd 0 IO L L 7 vdds_mmc1 Yes 8 PU/ PD (5) LVCMOS gpio_121 4 IO safe_mode 7 N27 NA mmc1_dat0 0 IO L L 7 vdds_mmc1 Yes 8 PU/ PD (5) LVCMOS gpio_122 4 IO safe_mode 7 N26 NA mmc1_dat1 0 IO L L 7 vdds_mmc1 Yes 8 PU/ PD (5) LVCMOS gpio_123 4 IO safe_mode 7 N25 NA mmc1_dat2 0 IO L L 7 vdds_mmc1 Yes 8 PU/ PD (5) LVCMOS gpio_124 4 IO safe_mode 7 P28 NA mmc1_dat3 0 IO L L 7 vdds_mmc1 Yes 8 PU/ PD (5) LVCMOS gpio_125 4 IO safe_mode 7 P27 NA mmc1_dat4 0 IO L L 7 vdds_mmc1a No 8 PD (5) LVCMOS gpio_126 4 IO safe_mode 7 P26 NA mmc1_dat5 0 IO L L 7 vdds_mmc1a No 8 PD (5) LVCMOS gpio_127 4 IO safe_mode 7 R27 NA mmc1_dat6 0 IO L L 7 vdds_mmc1a No 8 PD (5) LVCMOS gpio_128 4 IO safe_mode 7 R25 NA mmc1_dat7 0 IO L L 7 vdds_mmc1a No 8 PD (5) LVCMOS gpio_129 4 IO safe_mode 7 (3) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in the above table. (4) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in the above table. (5) The PU nominal drive strength of this IO cell is equal to 25 uA @ 1.8V and 41.6 uA @ 3.0V. The PD nominal drive strength of this IO cell is equal to 1 mA @ 1.8V and 1.66 mA @ 3.0V. Copyright © 2008–2013, Texas Instruments Incorporated TERMINAL DESCRIPTION 35 Submit Documentation Feedback Product Folder Links: OMAP3530 OMAP3525 |
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