| 数据搜索系统,热门电子元器件搜索 |
|
PL102-10SI-R 数据表(PDF) 5 Page - Micrel Semiconductor |
|
|
|||||||||||||||||||||||||||||
PL102-10SI-R 数据表(HTML) 5 Page - Micrel Semiconductor |
|
5 / 7 page ![]() PL102-10 Low Skew Output Buffer Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 5 Output-Output Skew REF CLKOUT The skew between CLKOUT and the CLK(1-2) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will be maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must be equally loaded. If the CLK(1-2) outputs are less loaded than CLKOUT, CLK(1-2) outputs will lead it; if the CLK(1-2) is more loaded than CLKOUT, CLK(1-2) will lag the CLKOUT. Since the CLKOUT and the CLK(1-2) outputs are identical, they all start at the same time, but difference loads cause them to have different rise times and different times crossing the measurement thresholds. CLK(1-2) Zero Delay REF CLKOUT CLK(1-2) Advanced REF CLKOUT CLK(1-2) Delayed REF input and all outputs are equally loaded REF input and CLK(1-2) outputs are equally loaded, with CLK(1-2) less loaded than CLKOUT. REF input and CLK(1-2) outputs loaded equally, withCLK(1-2) more loaded then CLKOUT. |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |