PL102-10SI-R datasheet(3/7 Pages) MICREL

3 / 7 page

PL102-10

Low Skew Output Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 3

3. Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input/Output Frequency

2.5V/3.3V

145/170

MHz

Duty Cycle

Measured at VDD/2, CL=15pF,

Fout = 100MHz

Rise Time

Measured between 10% and

90%VDD, CL=15pF

1.2

1.5

Fall Time

Measured between 90% and

10%, CL=15pF

1.2

1.5

Output to Output Skew

Tskew

All outputs equally loaded,

CL=15pF

200

Delay, REF Rising Edge

to CLKOUT Rising Edge

Tdelay

Measured at VDD/2

350

Device to Device Skew

Tdsk-dsk

Measured at VDD/2 on the

CLKOUT pins of devices

700

Cycle to Cycle Jitter

Tcyc-cyc

Measured at 100MHz

PLL Lock Time

Tlock

Stable power supply, valid

clock presented on REF pin

1.0

Jitter; Absolute Jitter

Tjabs

Measured 10,000 cycles,

low jitter input signal

Jitter; 1-sigma

Tj1-s

Measured 10,000 cycles,

low jitter input signal

SWITCHING WAVEFORMS

Duty Cycle Timing

VDD/2

Output - Output Skew

VDD/2

SKEW

Output

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