PL102-10

Low Skew Output Buffer

FEATURES

 Frequency Range:

− 15 to 170MHz @ 3.3V

− 15 to 145MHz @ 2.5V

 Internal Phase Locked Loop Allows Spread

Spectrum Modulation on Reference Clock to

Pass to Outputs.

 Zero Input to Output Delay

 Less Than 700ps Device to Device Skew

 Less Than 200ps Skew Between Outputs

 Less Than 100ps Cycle to Cycle Jitter

 2.5V or 3.3V Power Supply

 Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS

Compliant Packages

PIN CONFIGURATION

DESCRIPTION

The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed

clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the

input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between

the input and output is less than

350 ps, the device acts as a zero delay buffer.

BLOCK DIAGRAM

PLL

REFIN

CLKOUT

CLK1

CLK2

1

2

3

4

5

6

7

8

REFIN

CLK1

CLK2

CLKOUT

DNC

VDD

DNC

GND

SOP-8L

1

2

3

4

5

6

CLK1

GND

REFIN

CLK2

CLKOUT

VDD

SOT23-6L