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ADP5070

Data Sheet

Rev. A | Page 18 of 27

Output Capacitors

Higher output capacitor values reduce the output voltage ripple

and improve load transient response. When choosing this value,

it is also important to account for the loss of capacitance due to

the output voltage dc bias.

Ceramic capacitors are manufactured with a variety of dielectrics,

each with a different behavior over temperature and applied

voltage. Capacitors must have a dielectric adequate to ensure

the minimum capacitance over the necessary temperature range

and dc bias conditions. X5R or X7R dielectrics with a voltage rating

of 25 V or 50 V (depending on output) are recommended for

best performance. Y5V and Z5U dielectrics are not recommended

for use with any dc-to-dc converter because of their poor

temperature and dc bias characteristics.

Calculate the worst-case capacitance accounting for capacitor

variation over temperature, component tolerance, and voltage

using the following equation:

CEFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×

(1 − Tolerance)

where:

CEFFECTIVE is the effective capacitance at the operating voltage.

CNOMINAL is the nominal data sheet capacitance.

TEMPCO is the worst-case capacitor temperature coefficient.

DCBIASCO is the dc bias derating at the output voltage.

Tolerance is the worst-case component tolerance.

To guarantee the performance of the device, it is imperative that

the effects of dc bias, temperature, and tolerances on the behavior

of the capacitors be evaluated for each application.

Capacitors with lower effective series resistance (ESR) and

effective series inductance (ESL) are preferred to minimize

output voltage ripple.

Note that the use of large output capacitors can require a slower

soft start to prevent current limit during startup. A 10 µF capacitor

is suggested as a good balance between performance and size.

Input Capacitor

Higher value input capacitors help to reduce the input voltage

ripple and improve transient response.

To minimize supply noise, place the input capacitor as close as

possible to the PVINSYS pin, PVIN1 pin, and PVIN2 pin. A low

ESR capacitor is recommended.

The effective capacitance needed for stability is a minimum of 10 µF.

If the power pins are individually decoupled, it is recommended

to use an effective minimum of a 5.6 µF capacitor on the PVIN1

and PVIN2 pins and a 3.3 µF capacitor on the PVINSYS pin. The

minimum values specified exclude dc bias, temperature, and

tolerance effects that are application dependent and must be

taken into consideration.

VREG Capacitor

A 1.0 µF ceramic capacitor (CVREG) is required between the VREG

pin and AGND.

VREF Capacitor

A 1.0 µF ceramic capacitor (CVREF) is required between the VREF

pin and AGND.

Soft Start Resistor

A resistor can be connected between the SS pin and the AGND pin

to increase the soft start time. The soft start time can be set by

the resistor between 4 ms (268 kΩ) and 32 ms (50 kΩ). Leaving

the SS pin open selects the fastest time of 4 ms. Figure 44 shows the

behavior of this operation. Calculate the soft start time using the

following formula:

tSS = 38.4 × 10−3 − 1.28 × 10−7 × RSS (Ω)

where 50 kΩ ≤ RSS ≤ 268 kΩ.

SS PIN OPEN

SOFT START

TIMER

SOFT START

RESISTOR

32ms

4ms

Figure 44. Soft Start Behavior

Diodes

A Schottky diode with low junction capacitance is recommended

for D1 and D2. At higher output voltages and especially at higher

switching frequencies, the junction capacitance is a significant

contributor to efficiency. Higher capacitance diodes also generate

more switching noise. As a guide, a diode with less than 40 pF

junction capacitance is preferred when the output voltage is

above 5 V.

Inductor Selection for the Boost Regulator

The inductor stores energy during the on time of the power

switch, and transfers that energy to the output through the

output rectifier during the off time. To balance the tradeoffs

between small inductor current ripple and efficiency, inductance

values in the range of 1 µH to 22 µH are recommended. In general,

lower inductance values have higher saturation current and

lower series resistance for a given physical size. However, lower

inductance results in a higher peak current that can lead to reduced

efficiency and greater input and/or output ripple and noise. A peak-

to-peak inductor ripple current close to 30% of the maximum dc

input current for the application typically yields an optimal

compromise.

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