ADP5070AREZ-R7 datasheet(27/28 Pages) AD

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ADP5070

Data Sheet

Rev. A | Page 26 of 27

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators but is particularly

important for regulators with high switching frequencies. To

achieve high efficiency, good regulation, good stability, and low

noise, a well-designed PCB layout is required. Follow these

guidelines when designing PCBs:

•

Keep the input bypass capacitor, CIN1, close to the PVIN1 pin,

the PVIN2 pin, and the PVINSYS pin. Route each of these

pins individually to the pad of this capacitor to minimize

noise coupling between the power inputs rather than

connecting the three pins at the device. A separate capacitor

can be used on the PVINSYS pin for the best noise

performance.

•

Keep the high current paths as short as possible. These paths

include the connections between CIN1, L1, L2, D1, D2,

COUT1, COUT2, and PGND and their connections to the

ADP5070.

•

Keep AGND and PGND separate on the top layer of the

board. This separation avoids pollution of AGND with

switching noise. Do not connect PGND to the EPAD on

the top layer of the layout. Connect both AGND and PGND

to the board ground plane with vias. Ideally, connect PGND

to the plane at a point between the input and output

capacitors. Connect the EPAD on its own to this ground

layer with vias and connect AGND as near to the pin as

possible between the CVREF and CVREG capacitors.

•

Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and electromagnetic interference (EMI).

•

Avoid routing high impedance traces near any node con-

nected to the SW1 and SW2 pins or near Inductors L1and

L2 to prevent radiated switching noise injection.

•

Place the feedback resistors as close to the FB1 and FB2 pins as

possible to prevent high frequency switching noise injection.

•

Place the top of the upper feedback resistors, RFT1 and RFT2,

or route traces to them from as close as possible to the top

of COUT1 and COUT2 for optimum output voltage sensing.

•

Place the compensation components as close as possible to

COMP1 and COMP2. Do not share vias to the ground plane

with the feedback resistors to avoid coupling high frequency

noise into the sensitive COMP1 and COMP2 pins.

•

Place the CVREF and CVREG capacitors as close to the

VREG and VREF pins as possible. Ensure that short traces

are used between VREF and RFB2.

Figure 50. Suggested LFCSP Layout; Vias Connected to the PCB Ground

Plane, Not to Scale

Figure 51. Suggested TSSOP Layout; Vias Connected to the PCB Ground

Plane, Not to Scale

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