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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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MT9072AB 数据表(PDF) 4 Page - Zarlink Semiconductor Inc |
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MT9072AB 数据表(HTML) 4 Page - Zarlink Semiconductor Inc |
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4 / 275 page  MT9072 Data Sheet 4 Zarlink Semiconductor Inc. Common Channel Signaling Timeslot Assigner • Selected 64 Kbit/s CCS channels (for V5.2 and GR-303) can be routed to/from an external multichannel HDLC, using the CSTi/0 pins Access and Monitoring for National (Sa) Bits (E1 mode only) • In addition to the datalink functions, the Sa bits can be accessed using: • Single byte register • Five byte transmit and receive national bit buffers • A maskable interrupt is generated on the change of state of any Sa bit Slip Buffers • Operates at 4 kbit/s (FDL), 56 kbit/s or 64 kbit/s • Operates at 4, 8, 12, 16 or 20 kbit/s (Sa bits) or 64 kbit/s T1/J1 Mode E1 Mode Transmit Slip Buffer • Two-frame slip buffer capable of performing a controlled slip. Intended for rate conversion in the transmit direction Receive Slip Buffer • Two-frame slip buffer capable of performing a controlled slip • Wander tolerance of 208 UI peak-to-peak • Programmable delay • Indication of slip • Transmit slips are independent of receive slips • Indication of slip direction • Indication of slip • Indication of slip direction Receive Slip Buffer • Two-frame slip buffer capable of performing a controlled slip • Wander tolerance of 142 UI (92 µs) peak • Indication of slip • Indication of slip direction T1/J1 Mode E1 Mode |
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