MT9072AB datasheet(3/275 Pages) ZARLINK

3 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

Data Link

One Embedded Floating HDLC per Framer

• Flag generation and Frame Check Sequence (FCS) generation and detection, zero insertion and deletion

• Continuous flags, or continuous 1s are transmitted between frames

• Transmit frame-abort

• Invalid frame handling:

• Frames yielding an incorrect FCS are tagged as bad packets

• Frames with fewer than 25 bits are ignored

• Frames with fewer than 32 bits between flags are tagged as bad packets

• Frames interrupted by a Frame-Abort sequence remain in the FIFO and an interrupt is generated

• Access is provided to the receive FCS

• FCS generation can be inhibited for terminal adaptation

• Recognizes single byte, dual byte and all call addresses

• Independent, 32 byte deep transmit and receive FIFOs

• Receive FIFO maskable interrupts for nearly full and overflow conditions

• Transmit FIFO maskable interrupts for nearly empty and underflow conditions

• Maskable interrupts for transmit end-of–packet and receive end-of-packet

• Maskable interrupts for receive bad-frame (includes frame abort)

• Transmit-to-receive and receive-to-transmit loopbacks are provided

• Transmit and receive bit rates and enables are independent

• Frame aborts can be sent under software control and they are automatically transmitted in the event of a

transmit FIFO underrun

T1/J1 Mode

E1 Mode

•

Three methods are provided to access the

datalink:

1. TxDL and RxDL pins support transmit and

receive datalinks

2. Bit Oriented Messages are supported via

internal registers

3. An internal HDLC can be assigned to

transmit/receive over the FDL in ESF mode

•

Two methods are provided to access the

datalink:

1. TxDL and RxDL pins support transmit and

receive datalinks over the Sa4~Sa8 bits

2. An internal HDLC can be assigned to

transmit/receive data via the Sa4~Sa8 bits

•

In transparent mode, if the Sa4 bit is used for

an intermediate datalink, the CRC-4 remainder

can be updated to reflect changes to the Sa4

bit

T1/J1 Mode

E1 Mode

•

Assignable to the ESF Facility Data Link or any

other channel

•

Assignable to timeslot-0, bits Sa4~Sa8 or any

other timeslot

MT9072AB 数据表(PDF) 3 Page - Zarlink Semiconductor Inc

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