FEDL7066-01

ML7066

7/29

Other Pins

Pin No.

Pin Name

Attribute/

value at reset

I/O

Active

Level

Description

8

RESETN

I

L

Hardware reset pin

7

SRESETN

I

L

Software reset pin

Wake up pin when in sleep mode.

This pin is active when RESETN=1.

2

XI

I

P or N

19.2 MHz crystal connection pin 1

External clock input pin.

1

XO

O

–

19.2 MHz crystal connection pin 2

Leave open when XI (pin #2) is configured as an external clock

input pin.

9

SW_CTRL

O

L

Antenna switch control pin

L: In transmitting mode

HiZ: In receiving mode

47

POWOFF

L

O

H

External component power on/off control pin

Active level polarity is changeable by register setting.

48

EXTCLK

I

I

P or N External 32.768 kHz clock input pin (*3)

38

MODE1

I

IO

H or L

Bit order on SCI Data setting pin

L: LSB first

H: MSB first

39

MODE2

I

I

H or L

Operation mode setting pin

L: Normal mode

H: Test mode

Always fix this pin to “L” input in normal operation.

22,24

NC

O

–

Unused. (Open)

(*3) Always EXTCLK input is required for ML7066 operation.

Recommended Handling of Unused Pins

LAPIS Semiconductor recommends handling unused pins as shown below so that the basic operation of the ML7275 is

unimpaired.

Pin No.

Pin Name

Recommended pin handling

1

XO

Open (when XI is configured as an external clock input pin.)

7

SRESETN

Connect to VDDIO

47

POWOFF

Open

NOTE

If any input pins are left open, the current consumption may increase. Therefore, it is recommended that the unused

input ports and I/O ports be always fixed with “L” or “H” input.