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ML7066 数据表(PDF) 22 Page - LAPIS Semiconductor Co., Ltd.

部件名 ML7066
功能描述  400MHz Transceiver IC for Specified Low-Power Station
PDF  29 Pages
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制造商  LAPIS [LAPIS Semiconductor Co., Ltd.]
网页  http://www.lapis-semi.com/
标志 LAPIS - LAPIS Semiconductor Co., Ltd.

ML7066 数据表(HTML) 22 Page - LAPIS Semiconductor Co., Ltd.

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Transmit/Receive Data Interface Characteristics
(Operation power supply voltage: 2.1V - 3.6V, Ta=-25 - +65°C)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
DIO input setup time
TDISU
At transmission
20
—
—
ns
DIO input hold time
TDIH
At transmission
20
—
—
ns
DCLK output delay time
TDCKOD
At reception
—
—
40
ns
DIO output hold time
TDOH
At reception
Load
capacitance
CL= 50pF
15
—
—
ns
(Notes)
All the timings are measured at the 20% and 80% levels of VDDIO.
The DCLK clock frequency FDCLK is 600Hz / 1200Hz / 2400Hz / 4800Hz.
Reset Characteristics
(Operation power supply voltage: 2.1V - 3.6V, Ta=—25 - +65°C)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
RESETN delay time (at power on)
TRDL
After all power supply pins
are powered on
1
—
—
ms
SRESETN pulse time
TRPLS
RESETN=1
200
—
—
ns
SRESETN delay time (when operating)
TRDOP
1
—
—
ms
RESETN-SRESETN setup time
(when operating)
TRSU
10
—
—
ns
(Notes)
All the timings are measured at the 20% and 80% levels of VDDIO.
VDD
VDD voltage
level
GND level
RESETN
SRESETN
TRDO
TRDL
TRPL
TRSU
DCL
DIO
(At
reception)
DIO
(At
transmission)
VALID
VALID
VALID
VALID
VALID
TDCKOD
TDOH
FDCLK
TDIS
TDI
VALID
TDCKOD
FDCLK



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