ML7066 datasheet(5/29 Pages) LAPIS

部件名	ML7066

功能描述	400MHz Transceiver IC for Specified Low-Power Station

PDF	29 Pages

Scroll/Zoom	100%

制造商	LAPIS [LAPIS Semiconductor Co., Ltd.]

网页	http://www.lapis-semi.com/

标志

5 / 29 page

FEDL7066-01

ML7066

5/29

TX/RX Data Related Pins

Pin No. Pin Name

Attribute/

value at reset

I/O

Active

Level

Description

DIO

H or L

Data input/output pin (Initial value is Low when switch the state

from input to output)

DCLK

P or N Data clock output pin

Regulator Related Pins

Pin No.

Pin Name

Attribute/

value at reset

I/O

Active

Level

Description

VREG_OUT

–

Power supply output pin for the RF block (Typ. 2.2V)

Do not use this pin for purposes other than RF power supply.

VREG_CORE

–

Power supply monitor pin for the core (Typ. 2.2V)

Do not use this pin for purposes other than monitoring purpose.

Decuple this pin to ground with capacitor. (*1)

VBG

–

Back bias pin (Capacitance connection)

Decuple this pin to ground with capacitor. (*1)

REGPDIN

–

Regulator power down pin

Always fix this pin to “L” input in normal operation.

*1: Please refer reference circuit.

ML7066 数据表(PDF) 5 Page - LAPIS Semiconductor Co., Ltd.

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