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VDP313XY 数据表(PDF) 34 Page - Micronas

部件名 VDP313XY
功能描述  Video Processor Family
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICRONAS [Micronas]
网页  http://www.micronas.com
标志 MICRONAS - Micronas

VDP313XY 数据表(HTML) 34 Page - Micronas

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VDP 313xY
ADVANCE INFORMATION
34
Micronas
Picture Frame Generator
47
9
w v
bit[7:0]
reserved, set t o zero
bit[8]
1
enable picture frame generator
0
PFGEN
11
16
w h
picture frame color 12 bit wide,
bit[3:0]
0..15
blue amplitude
bit[7:4]
0..15
green amplitude
bit[11:8]
0..15
red amplitude
0
0
0
PFC
PFCB
PFCG
PFCR
4C
9
w v
picture frame insertion contrast for R
(ampl. range: 0 to 255)
bit[3:0]
reserved, set to zero
bit[7:4]
0..13
R amplitude =
PFCR
× (PFRCT + 4)
14,15
invalid
8
PFRCT
48
9
w v
picture frame insertion contrast for G
(ampl. range: 0 to 255)
bit[3:0]
reserved, set to zero
bit[7:4]
0..13
G amplitude =
PFCG
× (PFGCT + 4)
14,15
invalid
8
PFGCT
44
9
w v
picture frame insertion contrast for B
(ampl. range: 0 to 255)
bit[3:0]
reserved, set to zero
bit[7:4]
0..13
B amplitude =
PFCB
× (PFBCT + 4)
14,15
invalid
8
PFBCT
4F
9
w v
bit[8:0]
horizontal picture frame begin
code 0 = picture frame generator horizontally disabled
code 1FF = full frame
0PFGHB
53
9
w v
bit[8:0]
horizontal picture frame end
0
PFGHE
63
9
w v
bit[8:0]
vertical picture frame begin
code 0 = picture frame generator vertically disabled
270
PFGVB
6F
9
w v
bit[8:0]
vertical picture frame end
56
PFGVE
Priority Decoder
75
9
w v
bit[7]
0/1
select main/side setting for
contrast,brightness,matrix
0SIDE
79
9
w v
bit[7]
0/1
disable/enable peaking transient
suppression when signal is
switched to the picture frame
0
PKTRNS
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
(hex)
(hex)



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