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VDP313XY 数据表(PDF) 38 Page - Micronas

部件名 VDP313XY
功能描述  Video Processor Family
PDF  76 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICRONAS [Micronas]
网页  http://www.micronas.com
标志 MICRONAS - Micronas

VDP313XY 数据表(HTML) 38 Page - Micronas

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VDP 313xY
ADVANCE INFORMATION
38
Micronas
62
66
6A
9
9
9
w v
w v
w v
PLL2/3 filter coefficients, 1of5 bit code
(n+ set bit number)
bit[5:0]
proportional coefficient PLL3, 2−n−1
bit[5:0]
proportional coefficient PLL2, 2−n−1
bit[5:0]
integral coefficient PLL2, 2−n−5
2
1
2
PKP3
PKP2
PKI2
15
16
w/r
horizontal drive and vertical signal control register
bit[5:0]
0..63
horizontal drive pulse duration in
µs (internally limited to 4..61)
bit[6]
0/1
disable/enable horizontal PLL2
and PLL3
bit[7]
0/1
1: disable horizontal drive pulse
during flyback
bit[8]
0/1
reserved, set to ’0’
bit[9]
0/1
enable/disable ultra black
blanking
bit[10]
0/1
0: all outputs blanked
1: normal mode
bit[11]
0/1
enable/disable clamping for
analog RGB input
bit[12]
0/1
disable/enable vertical free
running mode (FIELD is set to
field2, no interlace)
bit[13]
0/1
enable/disable vertical protection
bit[14]
reserved (set to 0)
bit[15]
0/1
disable/enable phase shift of
display clock
32
0
0
0
0
1
0
0
0
0
1
HVC
HDRV
EHPLL
EFLB
DUBL
EBL
DCRGB
SELFT
DVPR
DISKA
9D
8
w/r
sync output control
bit[0]
invert INTLC
bit[1]
disable INTLC (tristateINTLC output)
bit[2]
invert VS
bit[3]
disable VS
bit[4]
disable CSY
bit[5]
force INTLC to polarity defined in
’INTLCINV’
0
SYCTRL
9E
8
w/r
delay of CSY output (relative to PLL2)
bit[7:0]
−128..127 ± 8 µs
0
CSYDEL
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode
Function
Default
Name
(hex)
(hex)



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