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ESDALC6V1W5 数据表(PDF) 5 Page - STMicroelectronics |
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ESDALC6V1W5 数据表(HTML) 5 Page - STMicroelectronics |
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5 / 9 page ![]() ESDALC6V1W5 5/9 V(i/o) TEST BOARD V(i/o) Fig. A2: ESD test board B2 I/O1, I/O2, I/O3 or I/O4 V(i/o) ± 8kV ESD Contact discharge Fig. A3: ESD test configuration The measurements done here after show very clearly (Fig. A4) the high efficiency of the ESD protection: the clamping voltage V(i/o) becomes very close to +VBR (positive way, Fig. A4a) and -VBR (negative way, Fig. A4b). Fig. A4: Remaining voltage during ESD surge V(i/o) V(i/o) a: Response in the positive way b: Response in the negative way |
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