11

LTC4350

4350fa

When the power supply is disconnected, the UV pin will

drop below 1.220V if the supply is loaded. The LTC4350

then discharges the gate of the power FET isolating the

load from the power supply.

DESIGN EXAMPLE

Load Share Components

This section demonstrates the calculations involved in

selecting the component values. The design example in

Figure 5 is a 5V output. This design can be extended to

each of the parallel sections.

The first step is to determine the final output voltage and

the amount of adjustment on the output voltage. The

power supply voltage before the load sharing needs to be

lower than the final output voltage. If the load is expecting

to see a 5V output, then all of the shared power supplies

need to be trimmed to 4.90V or lower. This allows 2%

variation in component and reference tolerances so that

the output always starts below 5V.

Now that the output voltage is preset below the desired

output, the LTC4350 will be responsible for increasing the

the module’s error amplifier can be used. The next step is

to determine the maximum positive adjustment needed for

each power supply. This adjustment includes any I • R drops

across sense resistors, power FETs, wiring and connec-

tors in the supply path between the power supply and the

load. For example, if the maximum current is 10A and the

parasitic resistance between the power supply and load is

0.01Ω, then the positive adjustment range for I • R drops

is 0.1V. Since the starting voltage is 4.9V ±0.1V, then the

lowest starting voltage can be 4.8V. This voltage is 0.2V

below the target. The total adjustment range that the

LTC4350 will need for this example is 0.1V + 0.2V = 0.3V.

Note that the lowest starting voltage should not be lower

than 300mV below the target voltage.

The I • R drops should be designed to be low to eliminate

the need for additional bulk capacitance at the load. In

most cases the bulk capacitance exists at the power

supply output before the I • R drops. If a 0.002Ω sense

resistor is used and the FET resistance is below 0.003Ω,

then a total 0.005Ω series resistance is acceptable for

loads to 20A. Obviously, the FB pin compensates for the

DC output impedance, but the AC output impedance is the

I • R drops plus the ESR of the capacitors.

APPLICATIO S I FOR ATIO

4

3

2

1

86.6k

100Ω

GAIN

FB

TIMER

0.1µF

STATUS

STATUS

4350 F05

SB

COMP1

GATE

GND

COMP2

LTC4350

UV

OV

1000pF

1µF

150Ω

43.2k

274k

12.1k

121k

0.1µF

0.1µF

4.9V NOMINAL, 5.3V MAXIMUM

100Ω

0.002Ω

37.4k

5V

BUS

12.1k

30Ω

51Ω

4 × SUD50N03-07

(0.007Ω EACH)

SHARE

BUS

0.1µF

Figure 5. 5V Load Share (20A per Module)