LTC4350IGN datasheet(12/16 Pages) LINER

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LTC4350

4350fa

The resistors ROUT and RSET set the adjustment range. The

voltage on RSET is translated to a voltage on ROUT by the

ratio of ROUT/RSET. Therefore, the adjustment on the

output voltage will track the voltage at the RSET pin which

is also the voltage on the COMP2 pin minus a diode

voltage. The expression is VADJ = (VRSET) • ROUT/RSET =

(VCOMP2 – VDIODE) • ROUT/RSET. The maximum voltage at

VRSET is limited to 1V. The maximum adjustment on the

output is expressed as VADJMAX = ROUT/RSET. A normal

value for RSET is in the 50Ω to 100Ω range.

If we set RSET to be 100Ω, then an ROUT of 100Ω allows

the output voltage a full 1V adjustment. For the 0.3V range

in this example, the ROUT is 30Ω. In some power modules,

there already exists a resistor between the SENSE+ line

and the power output. In this case, the value of ROUT is the

parallel combination of two resistors, one in the module

and one placed between the SENSE+ and output terminals

of the module.

The value of the gain setting resistor, RGAIN, depends on

the maximum voltage drop across the sense resistor and

the supply voltage VCC for the chip. The highest possible

voltage at the GAIN pin is 1.5V from the VCC voltage. The

maximum voltage on the GAIN pin is expressed as:

VGAINMAX = RSENSE • IMAX • RGAIN/1k = VCC – 1.5V. The

expression for RGAIN: RGAIN = (VCC – 1.5V) • 1k/(RSENSE •

IMAX). In this example, VCC is 5V, IMAX is 20A and RSENSE

is 0.002Ω. Therefore, RGAIN is 87.5k but using 1% values

results in 86.6k.

The FB pin divider provides a 1.220V output for a 5V input.

The precision of the FB pin divider resistors will impact the

accuracy of the final output voltage. The UV resistive

divider in this example, turns on the gate when VCC

increases above 4V. This corresponds to the UV pin at

1.220V. The capacitor CUV prevents false activation during

load steps. The OV set point needs to occur above the

adjustment max for VCC. The power supply output (which

also is VCC), can start as high as 5V and adjust upwards to

5.3V. The OV set point in this example is 5.5V on VCC when

the OV pin is at 1.220V.

The timer capacitor CT is set to be 0.1µF for a 61ms timer

cycle. The expression is t = CT • 1.22V/2µA. The gate

capacitor CG is set to be 0.1µF which sets a slope of 10µA/

CG or 1V every 10ms. In this case, the GATE pin must

charge up to 9V before the output can ramp to 5V which

happens in 90ms. In this case, the output adjust soft-start

turns on when the gate ramps above 9V. The soft-start

circuitry releases the COMP2 pin allowing the load sharing

loop to function. A 100Ω resistor RG prevents high fre-

quency oscillations from the power FETs at their turn-on

threshold. A 0.1µF bypass capacitor is required on the VCC

pin. If the VCC pin is tied to the same power supply output

that is being adjusted, then a 51Ω decoupling resistor is

needed to hold up the supply during a short to ground on

the supply output.

COMPENSATION

The compensation capacitor, CP1, is needed to set the

crossover frequency of the feedback error amplifier E/A1.

The crossover frequency of 200kHz is adequate for most

applications and requires CP1 to be 1000pF (0.001µF).

The design of the other compensation capacitor will

require some knowledge about the power supply’s band-

width. The bandwidth can be measured easily. First, use

a storage oscilloscope to monitor the power supply

output voltage. Then place a 1A resistive fixed load and

switch in a second resistive load that increases the total

load current close to rated maximum. Tapping the second

resistor (with the correct power rating) to the power

supply output creates this load step. Trigger the scope on

the falling edge of the output voltage as it drops more than

100mV (for example from 5V to 4.8V). The recovery time,

tR, from the step needs to be measured. tR is defined as

the 10% to 90% time measurement (see Figure 6). The

APPLICATIO S I FOR ATIO

4350 F06

0.1∆V

∆V

0.1∆V

90%

10%

Figure 6. tR Measurement

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