5

LTC4350

4350fa

PI FU CTIO S

COMP2 (Pin 5): Analog Output Pin. This pin is the output

of the share bus error amplifier E/A2. (A compensation

capacitor between this pin and ground sets the crossover

frequency for the power supply adjustment loop.) In most

cases, this pin operates between 0.5V to 1.5V and repre-

It is clamped at 3V. During start-up, this pin is clamped to

ground. After a timer cycle (and if the GATE pin is high), the

COMP2 pin is released.

COMP1 (Pin 6): Analog Output Pin. This pin is the output

of the voltage regulating error amplifier E/A1. A compen-

sation capacitor between this pin and ground sets the

crossover frequency of the share bus loop. This pin

operates a diode voltage up from the voltage at the SB pin

and is clamped at 8.4V.

SB (Pin 7): Analog Output Pin. This pin drives the share

bus used to communicate the value of shared load current

between several power supplies. There is an amplifier that

drives this pin a diode below the COMP1 pin using an

internal NPN as a pull-up and a 20k resistor as a pull-down.

GND (Pin 8): Chip Ground.

FB (Pin 9): Analog Error Amplifier Input (E/A1). This pin is

used to monitor the output supply voltage with an external

resistive divider. The FB pin voltage is compared to 1.220V

reference. The difference between the FB pin voltage and

the reference is amplified and output on the COMP1 pin.

converts the voltage at the COMP2 pin (down a diode

adjust the output voltage.

is used to adjust the output supply voltage by modifying

the voltage sensed by the power supply’s internal voltage

feedback circuitry.

multiplied at the GAIN pin.

multiplied at the GAIN pin.

GATE (Pin14): The high side gate drive for the external

N-Channel power FET. An internal charge pump provides

the gate drive necessary to drive the FETs. The slope of the

voltage rise or fall at the GATE is set by an external

capacitor connected between GATE and GND, and the

10µA charge pump output current. When the undervoltage

high or the UV pin is pulled low, the GATE pin is immedi-

ately pulled to GND.

STATUS (Pin 15): Open-Drain Digital Output. The STA-

TUS pin has an open-drain output to GND. This pin is

pulled low to indicate a fault has occurred in the system.

There are three types of faults. The first is a undervoltage

voltage is active. The second is when the COMP2 pin is

above 1.5V or below 0.5V and the voltage on the GAIN pin

is greater than 100mV. The final failure is when the OV pin

is high. The three faults will activate the pull-down on the

STATUS pin after a timing cycle.

An undervoltage lockout circuit disables the chip until the

to the same power supply output that is being adjusted,

then a 51Ω decoupling resistor is needed to hold up the

must be greater than or equal to the supply that is