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CS89712 数据表(PDF) 76 Page - Cirrus Logic |
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CS89712 数据表(HTML) 76 Page - Cirrus Logic |
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76 / 170 page  CS89712 76 DS502PP2 generates an interrupt when the associated receive event occurs, but then does not accept the receive frame (the receive frame length is set to zero). The other five Accept bits in RxCTL are used for destination address filtering (see Section 2.32.7, “Receive Ethernet Port Locations”). The Accept mechanism is explained in more detail in Section 2.32, “Basic Receive Operation”. 3.2.7 Status/Control Register Summary This section gives a detailed description of each Status and Control register. Bits marked “RSVD” are reserved and must be written with a zero for proper operation of the device. |
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