CS89712 datasheet(94/170 Pages) CIRRUS

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CS89712

DS502PP2

Value

No. of Wait States

Random

No. of Wait States

Sequential

Table 46. Values of the Wait State Field at 18 MHz

Bit 3

Bit 2

Bit 1

Bit 0

Wait States

Random

Wait States

Sequential

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

Table 47. Values of the Wait State Field at 36 MHz

Bit

Description

SQAEN: Sequential access enable. Setting this bit will enable sequential accesses that are on a

quad word boundary to take advantage of faster access times from devices that support page

mode. The sequential access will be faulted after four words (to allow video refresh cycles to

occur), even if the access is part of a longer sequential access. In addition, when this bit is not

set, non-sequential accesses will have a single idle cycle inserted at least every four cycles so

that the chip select is de-asserted periodically between accesses for easier debug.

CLKENB: Expansion clock enable. Setting this bit enables the EXPCLK to be active during

accesses to the selected expansion device. This will provide a timing reference for devices that

need to extend bus cycles using the EXPRDY input. Back-to-back (but not necessarily page

mode) accesses will result in a continuous clock.

Table 48. MEMCFG

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