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CS89712 数据表(PDF) 85 Page - Cirrus Logic |
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CS89712 数据表(HTML) 85 Page - Cirrus Logic |
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85 / 170 page ![]() CS89712 DS502PP2 85 3.5.3 SYSCON3 System Control Register 3 (address 0x8000.2200) This register allows additional control for the CS89712. The bits of this register are defined in Table 38. 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved Reserved ENPD67 128Fs FASTWAKE 76 5 4 3 2 1 0 VERSN[2] Reserved VERSN[1] Reserved VERSN[0] Reserved ADCCKNSEN DAISEL CLKCTL1 CLKCTL0 ADCCON Bit Description 0 ADCCON: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be used for ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte SYNCIO(7:0) only is used for compatibility with the CL-PS7111. When this bit = 1, the ADC Con- figuration Extension field in the SYNCIO register is used for ADC Configuration data and the value in the ADC Configuration Byte (SYNCIO(6:0)) selects the length of the data (8-bit to 16-bit). 1:2 CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling. The table below lists the available options. Note: To determine the number of wait states programmed refer to Table 46 and Table 47. Under no circumstances should the CLKCTL bits be changed using a buffered write. 3 DAISEL: When set selects the DAI Interface. When cleared selects either the SSI or telephony codec interface (i.e., DAISEL bit is default low). 4 ADCCKNSEN: When set, configuration data is transmitted on ADCOUT at the rising edge of the ADCCLK, and data is read back on the falling edge on the ADCIN pin. When clear (default), the opposite edges are used. 5:7 VERSN[0:2]: Additional read-only version bits — will read ‘000’ 8 Reserved. This bit must be set to zero 9 128Fs: When set, this selects the 128 fs mode. Cleared by default to enable 64 fs operation. 10 ENPD67: Pd[6-7] control the byte mask of the SDRAM interface. Setting of this bit allows their use as GPIO bits for applications not using SDRAM. Table 39. SYSCON3 CLKCTL(1:0) Value Processor Frequency Memory Bus Frequency Wait State Scaling 00 18.432 MHz 18.432 MHz 1 01 36.864 MHz 36.864 MHz 2 10 49.152 MHz 36.864 MHz 2 11 73.728 MHz 36.864 MHz 2 |
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