STM8AL3LE8x datasheet(85/133 Pages) STMICROELECTRONICS

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STM8AL31E8x STM8AL3LE8x

Electrical parameters

119

9.3.4

Clock and timing characteristics

HSE external clock (HSEBYP = 1 in CLK_ECKCR)

Subject to general operating conditions for VDD and TA.

5. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.

Not tested in production.

6. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.

Not tested in production.

7. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and

the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.

Not tested in production.

8. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.

9. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.

10. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of

VDD /2. Floating DAC output.

11. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2

enabled with static inputs. Supply current of internal reference voltage excluded.

12. Including supply current of internal reference voltage.

Table 29. Current consumption under external reset

Symbol

Parameter

Conditions

Typ.

Unit

IDD(RST)

Supply current under

external reset (1)

PB1/PB3/PA5 pins are

externally tied to VDD

VDD = 1.8 V

µA

VDD = 3 V

VDD = 3.6 V

1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.

PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.

Table 30. HSE external clock characteristics

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

fHSE_ext(1)

External clock source

frequency

MHz

VHSEH

OSC_IN input pin high-

level voltage

0.7 x VDD

-VDD

VHSEL

OSC_IN input pin low-

level voltage

VSS

0.3 x VDD

Cin(HSE)(1) OSC_IN input capacitance

2.6

ILEAK_HSE

OSC_IN input leakage

current

VSS < VIN < VDD

±500

1. Guaranteed by design.

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