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STM8AL3L8x 数据表(PDF) 97 Page - STMicroelectronics |
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STM8AL3L8x 数据表(HTML) 97 Page - STMicroelectronics |
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97 / 131 page  DocID027179 Rev 6 97/131 STM8AL318x STM8AL3L8x Electrical parameters 117 Figure 36. Typical NRST pull-up current Ipu vs. VDD The reset network shown in Figure 37 protects the device against parasitic resets. The user must ensure that the level on the NRST pin goes below the VIL max. level specified in Table 45. Otherwise the reset is not taken into account internally. For power consumption- sensitive applications, the capacity of the external reset capacitor has to be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nF. Figure 37. Recommended NRST pin configuration |
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