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STM32F412RG 数据表(PDF) 129 Page - STMicroelectronics |
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STM32F412RG 数据表(HTML) 129 Page - STMicroelectronics |
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129 / 193 page  DocID028087 Rev 4 129/193 STM32F412xE/G Electrical characteristics 161 Figure 40. SPI timing diagram - slave mode and CPHA = 0 ta(SO) Data output access time Slave mode 7 - 21 ns tdis(SO) Data output disable time Slave mode 5 - 12 ns tv(SO) Data output valid time Slave mode (after enable edge), 2.7 V < VDD < 3.6 V -7.5 9 ns Slave mode (after enable edge), 1.7 V < VDD < 3.6 V -7.5 14 ns th(SO) Data output hold time Slave mode (after enable edge), 1.7 V < VDD < 3.6 V 5.5 - - ns tv(MO) Data output valid time Master mode (after enable edge) - 3 8 ns th(MO) Data output hold time Master mode (after enable edge) 2 - - ns 1. Guaranteed by characterization, not tested in production. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50% Table 64. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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