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STM32F412RG 数据表(PDF) 146 Page - STMicroelectronics |
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STM32F412RG 数据表(HTML) 146 Page - STMicroelectronics |
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146 / 193 page  Electrical characteristics STM32F412xE/G 146/193 DocID028087 Rev 4 Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 50 through Figure 53 represent asynchronous waveforms and Table 83 through Table 90 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 0x1 • AddressHoldTime = 0x1 • DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. Figure 50. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. |
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