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STM32F401CDU6 数据表(PDF) 7 Page - STMicroelectronics

部件名 STM32F401CDU6
功能描述  ARM Cortex-M4 32b MCUFPU, 105 DMIPS, 256KB Flash/64KB RAM, 11 TIMs, 1 ADC, 11 comm. interfaces
PDF  135 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F401CDU6 数据表(HTML) 7 Page - STMicroelectronics

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List of figures
STM32F401xB STM32F401xC
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List of figures
Figure 1.
Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2.
Compatible board design for LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3.
STM32F401xB/STM32F401xC block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4.
Multi-AHB matrix
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5.
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 19
Figure 6.
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7.
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 8.
Startup in regulator OFF: slow VDD slope -
power-down reset risen after VCAP_1/VCAP_2 stabilization. . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9.
Startup in regulator OFF mode: fast VDD slope -
power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10.
STM32F401xB/STM32F401xC WLCSP49 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11.
STM32F401xB/STM32F401xC UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 12.
STM32F401xB/STM32F401xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13.
STM32F401xB/STM32F401xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 14.
STM32F401xB/STM32F401xC UFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15.
Memory map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 16.
Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 17.
Input voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 18.
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 19.
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 20.
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 21.
Typical VBAT current consumption (LSE and RTC ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22.
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 23.
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 24.
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 25.
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 26.
ACCHSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 27.
ACCLSI versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 28.
PLL output clock waveforms in center spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 29.
PLL output clock waveforms in down spread mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 30.
FT I/O input characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 31.
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 32.
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 33.
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34.
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 35.
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 36.
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 37.
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 38.
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 39.
USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 104
Figure 40.
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 41.
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 42.
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 109
Figure 43.
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 110
Figure 44.
SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 45.
SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 46.
WLCSP49 - 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . 114



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