USB5744

DS00001855D-page 38

 2015-2016 Microchip Technology Inc.

9.7

Clock Specifications

The device can accept either a 25MHz crystal or a 25MHz single-ended clock oscillator (±50ppm) input. If the single-

ended clock oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be

driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(XTALI/XTALO). The following circuit design (Figure 9-6) and specifications (Table 9-10) are required to ensure proper

operation.

9.7.1

CRYSTAL SPECIFICATIONS

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(XTALI/XTALO). Refer to Table 9-10 for the recommended crystal specifications.

Note 6:

Frequency Deviation Over Time is also referred to as Aging.

FIGURE 9-6:

25MHZ CRYSTAL CIRCUIT

TABLE 9-10:

CRYSTAL SPECIFICATIONS

Parameter

Symbol

Min

Nom

Max

Units

Notes

Crystal Cut

AT, typ

Crystal Oscillation Mode

Fundamental Mode

Crystal Calibration Mode

Parallel Resonant Mode

Frequency

-

25.000

-

MHz

-

-

±50

PPM

Note 6

Frequency Stability Over Temp

-

-

±50

PPM

Note 6

Frequency Deviation Over Time

-

±3 to 5

-

PPM

Total Allowable PPM Budget

-

-

±100

PPM

Note 7

Shunt Capacitance

-

7 typ

-

pF

Load Capacitance

-

20 typ

-

pF

Drive Level

100

-

-

uW

Equivalent Series Resistance

--

50

Ω

Operating Temperature Range

Note 7

-

Note 8

XTALI/CLK_IN Pin Capacitance

-

3 typ

-

pF

Note 9

XTALO Pin Capacitance

-

3 typ

-

pF

Note 9

USB5742

XTALO

XTALI

Y1