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DS00002119A-page 11

USB2601/USB2602

5.0

PIN DESCRIPTIONS

This section provides a detailed description of each signal. The signals are arranged in functional groups according to

their associated interface.

The “n” or “_N” symbol in the signal name indicates that the active, or asserted state occurs when the signal is at a low

voltage level. When “n” is not present before the signal name (or “_N” after the signal name), the signal is asserted when

at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of

“active low” and “active high” signal. The term assert, or assertion indicates that a signal is active, independent of

whether that level is represented by a high or low voltage. The term negate, or negation indicates that a signal is inactive.

5.1

PIN Descriptions

Name

Symbol

Buffer Type

Description

UPSTREAM USB INTERFACE

USB Bus Data

USBUP_DM

USBUP_DP

IO-U

These pins connect to the Upstream USB bus data

signals.

Detect Upstream

VBUS Power

VBUS_DET

I/O12

Detects state of Upstream VBUS power. The Microchip

Hub monitors VBUS_DET to determine when to assert

the internal D+ pull-up resistor (signalling a connect

event).

When designing a detachable hub, this pin must be

connected to the VBUS power pin of the USB port that is

upstream of the hub.

For self-powered applications with a permanently

attached host, this pin must be pulled-up to either 3.3V or

5.0V (typically VDD33).

3-PORT USB INTERFACE

USB Bus Data

USBDN_DM

[4:2]

USBDN_DP

[4:2]

IO-U

These pins connect to the Downstream USB bus data

signals.

USB Power Enable

PRTPWR[4:2]

I/O12

Enables power to USB peripheral devices (downstream).

The active signal level of the PRTPWR[4:2] pins is

determined by the Power Polarity Strapping function of

the PRTPWR_POL pin.

Port Power Polarity

Strapping

PRTPWR_POL

I/O12

Port Power Polarity strapping determination for the active

signal polarity of the PRTPWR[4:2] pins.

While RESET_N is asserted, the logic state of this pin will

(though the use of internal combinatorial logic) determine

the active state of the PRTPWR[4:2] pins in order to

ensure that downstream port power is not inadvertently

enabled to inactive ports during a hardware reset.

‘1’ = PRTPWR[4:2] pins have an active ‘high’ polarity

‘0’ = PRTPWR[4:2] pins have an active ‘low’ polarity

Over Current Sense

OCS[4:2]_N

IPU

Input from external current monitor indicating an over-

current condition. {Note: Contains internal pull-up to 3.3V

supply}

Green LED

GR[4:2]_N

I/O8

Green indicator LED for ports 2, 3 and 4. Will be active

low when LED support is enabled via EEPROM or

SMBus.

CompactFlash (In True IDE mode) INTERFACE

CF Chip Select 1

CF_nCS1

O8PU

This pin is the active low chip select 1 signal for the CF

ATA device