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DS000002249A-page 21

USB2503/USB2503A

5.3.5

STRETCHING THE SCLK SIGNAL

The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch the SCLK.

5.3.6

SMBUS TIMING

The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in the “Timing

Diagram” section.

5.3.7

BUS RESET SEQUENCE

The SMBus Slave Interface resets and returns to the idle state upon a START field followed immediately by a STOP

field.

5.3.8

SMBUS ALERT RESPONSE ADDRESS

The SMBALERT# signal is not supported by the Hub.

5.3.9

INTERNAL SMBUS MEMORY REGISTER SET

The following table provides the SMBus slave interface register map values.

Note:

Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its

communications port after a start or stop condition.

TABLE 5-4:

SMBUS SLAVE INTERFACE REGISTER MAP

Reg

Addr

R/W

Register Name

Abbr

Bit 7

(MSb)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSb)

00h

R/W

Status/Command

STCD

7

6

5

4

3

2

1

0

01h

R/W

VID LSB

VIDL

7

6

5

4

3

2

1

0

02h

R/W

VID MSB

VIDM

7

6

5

4

3

2

1

0

03h

R/W

PID LSB

PIDL

7

6

5

4

3

2

1

0

04h

R/W

PID MSB

PIDM

7

6

5

4

3

2

1

0

05h

R/W

DID LSB

DIDL

7

6

5

4

3

2

1

0

06h

R/W

DID MSB

DIDM

7

6

5

4

3

2

1

0

07h

R/W

Config Data Byte 1

CFG1

7

6

5

4

3

2

1

0

08h

R/W

Config Data Byte 2

CFG2

7

6

5

4

3

2

1

0

09h

R/W

Non-Removable

Devices

NRD

7

6

5

4

3

2

1

0

0Ah

R/W

Port Disable (Self)

PDS

7

6

5

4

3

2

1

0

0Bh

R/W

Port Disable (Bus)

PDB

7

6

5

4

3

2

1

0

0Ch

R/W

Max Power (Self)

MAXPS

7

6

5

4

3

2

1

0

0Dh

R/W

Max Power (Bus)

MAXPB

7

6

5

4

3

2

1

0

0Eh

R/W

Hub Controller Max

Current (Self)

HCMCS

7

6

5

4

3

2

1

0

0Fh

R/W

Hub Controller Max

Current (bus)

HCMCB

7

6

5

4

3

2

1

0

10h

R/W

Power-on Time

PWRT

7

6

5

4

3

2

1

0