USB2503 datasheet(10/42 Pages) MICROCHIP

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USB2503/USB2503A

DS000002249A-page 10

 2007 - 2016 Microchip Technology Inc.

RESET Input

RESET_N

This active low signal is used by the system to reset the

chip. The minimum active low pulse is 100ns.

Self-Power /

Bus-Power

Detect

SELF_PWR

Detects availability of local self-power source.

Low = Self/local power source is NOT available (i.e., 7-

Port Hub gets all power from Upstream USB VBus).

High = Self/local power source is available.

TEST Pins

TEST[1:0]

IPD

Used for testing the chip. User must treat as a no-connect

or connect to ground. For board testing, all signal pins are

included in an XNOR chain, Please see 6.0, "XNOR Test,"

on page 30 for more details on the configuration and use

of the XNOR mode.

Analog Test

Internal 1.8V

voltage regulator

enable

ATEST/

REG_EN

AIO

This signal is used for testing the analog section of the

chip, and to enable or disable the internal 1.8v regulator.

This pin must be connected to VDDA3P3 to enable the

internal 1.8V regulator, or to VSS to disable the internal

regulator.

When the internal regulator is enabled, the 1.8V power

pins must be left unconnected, except for the required

bypass capacitors.When the PHY is in test mode, the

internal regulator is disabled and the ATEST pin functions

as a test pin.

TABLE 4-4:

POWER, GROUND, AND NO CONNECT

Name

Symbol

Type

Function

VDD1P8

VDD18

+1.8V core power.

If the internal regulator is enabled, then VDD18 pin

closest to VDD33CR must have a 4.7

F (or greater) ±20%

(ESR <0.1

capacitor to VSS

VDDPLL1P8

VDDA18PLL

+1.8V Filtered analog power for internal PLL.

If the internal regulator is enabled, then this pin must have

a 4.7

F (or greater) ±20% (ESR <0.1capacitor to VSS

VDDAPLL3P3

VDDA33PLL

+3.3V Filtered analog power for the internal PLL

If the internal PLL 1.8V regulator is enabled, then this pin

acts as the regulator input

VDDA3P3

VDDA33

+3.3V Filtered analog power.

VDD3P3

CORE

PLL

VDD33CR

+3.3V I/O and Core power.

VSS

Ground.

TABLE 4-5:

BUFFER TYPE DESCRIPTIONS

Buffer

Description

Input.

IPD

Input, with a weak Internal pull-down.

IPU

Input, with a weak Internal pull-up.

Input with Schmitt trigger.

O12

Output 12mA.

I/O12

Input/Output, 12mA

TABLE 4-3:

MISCELLANEOUS PINS (CONTINUED)

Name

Symbol

Type

Function

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