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AS29F010 数据表(PDF) 14 Page - Micross Components |
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AS29F010 数据表(HTML) 14 Page - Micross Components |
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14 / 26 page ![]() FLASH AS29F010 Micross Components reserves the right to change products or specifications without notice. 14 AS29F010 Rev. 2.6 11/10 TABLE 6: TEST CONDITIONS, Test Specifications CONDITIONS ALL SPEEDS UNIT Output Load Output Load Capacitance, CL (including jig capacitance) 50 pF Input Rise and Fall Times 5 ns Input Pulse Levels 0/3 V Input timing measurement reference levels 1.5 V Output timing measurement reference levels 1.5 V 1 TTL Gate AC CHARACTERISTICS: Read-Only Operations FIGURE 7: TEST CONDITIONS, Test Setup JEDEC Std -50 -60 -70 90 -120 -150 Read Cycle Time 1 tAVAV tRC MIN 50607090 120 150 ns Address to Output Delay tAVQV tACC CE\ = VIL OE\ = VIL MAX 50 60 70 90 120 150 ns Chip Enable to Output Delay tELQV tCE OE\ = VIL MAX 50 60 70 90 120 150 ns Output Enable to Output Delay tGLQV tOE MAX 25 30 35 40 50 55 ns Chip Enable to Output High Z 1 tEHQZ tDF MAX 15 20 20 25 30 35 ns Output Enable to Output High Z 1 tGHQZ tDF MAX 15 20 20 25 30 35 ns Read MIN ns Toggle and Data Polling MIN ns Output Hold Time From Addresses CE\ or OE\, Whichever Occurs First tAXQX tOH MIN ns PARAMETER TEST SETUP Output Enable Hold Time 1 tOEH SYMBOL UNITS 0 10 0 SPEED OPTIONS NOTES: 1. Not 100% tested. 2. See Figure 7 and Table 6 for test specifications. |
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