FLASH

AS29F040

Micross Components reserves the right to change products or specifications without notice.

4

AS29F040

Rev. 2.3 01/10

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the inter-

nal command register. The command register itself does not

occupy any addressable memory location. The register is

composed of latches that store the commands, along with the

address and data information needed to execute the command.

The contents of the register serve as inputs to the internal state

machine. The state machine outputs dictate the function of

the device. The appropriate device bus operations table lists

the inputs and control levels required, and the resulting output.

The following subsections describe each of these operations in

further detail.

Requirements for Reading Array Data

To read array data from the outputs, the system must drive

the CE\ and OE\ pins to V

selects the device. OE\ is the output control and gates array

data to the output pins. WE\ should remain at V

The internal state machine is set for reading array data upon

device power-up, or after a hardware reset. This ensures that

no spurious alteration of the memory content occurs

during

the power transition. No command is necessary in this mode

to obtain array data. Standard microprocessor read cycles that

assert valid addresses on the device address inputs

produce

valid data on the device data outputs. The device remains en-

abled for read access until the command register contents are

altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifications and

to the Read Operations Timings diagram for the timing wave-

forms. I

current specification for reading array data.

TABLE 1: DEVICE BUS OPERATIONS

Writing Commands/Command Sequences

To write a command or command sequence (which includes

programming data to the device and erasing sectors of memory),

the system must drive WE\ and CE\ to V

An erase operation can erase one sector, multiple sectors,

or the entire device. The Sector Address Tables indicate the

address space that each sector occupies. A “sector address” con-

sists of the address bits required to uniquely select a

sector.

See the “Command Definitions” section for details on erasing

a sector or the entire chip, or suspending/resuming the erase

operation.

After the system writes the autoselect command sequence,

the device enters the autoselect mode. The system can then read

autoselect codes from the internal register (which is

separate

from the memory array) on DQ7 - DQ0. Standard read cycle

timings apply in this mode. Refer to the “Autoselect Mode”

and “Autoselect Command Sequence” sections for more infor-

mation.

I

current specification for the write mode. The “AC

Char-

acteristics” section contains timing specification tables and

timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status bits

on DQ7 - DQ0. Standard read cycle timings and I

specifications apply. Refer to “Write Operation Status” for

more information, and to each AC Characteristics section for

timing diagrams.

Standby Mode

OPERATION

CE\

OE\

WE\

A0 - A20

DQ0 - DQ7

Read

L

L

H

Write

L

H

L

CMOS Standby

X

X

X

High-Z

TTL Standby

H

X

X

X

High-Z

Output Disable

L

H

H

X

High-Z