FLASH

AS29F040

Micross Components reserves the right to change products or specifications without notice.

2

AS29F040

Rev. 2.3 01/10

GENERAL DESCRIPTION

The AS29F040 is a 4Mbit, 5.0 Volt-only FLASH memory

organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of

data are divided into eight sectors of 64 Kbytes each for flex-

ible erase capability. The 8 bits of data appear on DQ0-DQ7.

The device is designed to be programmed in-system with the

standard system 5.0 Volt V

required for write or erase operations. The device can also be

programmed in standard EPROM programmers.

This device is manufactured using 0.32 μm process

technology. In addition, it has a second toggle bit, DQ2, and

offers the ability to program in the Erase Suspend mode.

It is available with access times of 55, 60, ^+^+6=70, 90,

120, and 150ns, allowing high-speed microprocessors to oper-

ate without wait states. To eliminate bus contention the device

has separate chip enable (CE\), write enable (WE\), and output

enable (OE\) controls.

The device requires only a single 5.0 volt power supply

for both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The device is entirely command set compatible with the

JEDEC single-power-supply FLASH standard. Commands are

written to the command register using standard microprocessor

write timings. Register contents serve as input to an internal

state-machine that controls the erase and programming circuitry.

Write cycles also internally latch addresses and data needed for

the programming and erase operations. Reading data out of

the device is similar to reading from other FLASH or EPROM

devices.

Device programming occurs by executing the program

command sequence. This invokes the Embedded Program

algorithm -- an internal algorithm that automatically times the

program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command

sequence. This invokes the Embedded Erase algorithm -- an

internal algorithm that automatically preprograms the array

(if it is not already programmed) before executing the erase

operation. During erase, the device automatically times the

erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase

operation is complete by reading the DQ7 (Data\Polling) and

DQ6 (toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data or accept

another command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data contents

of other sectors. The device is fully erased when shipped from

the factory.

The hardware data protection measures include a low

V

during power transitions. The hardware sector protection

feature

disables both program and erase operations in any

combination of the sectors of memory. This can be achieved

via programming equipment.

The erase suspect feature enables the user to put erase on

hold for any period of time to read data from, or program data

to, any sector that is not selected for erasure. True background

erase can thus be achieved.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode. The

device electrically erases all bits within a sector simultaneously

via Fowler-Nordheim tunneling. The data is programmed using

hot electron injection.

PIN CONFIGURATION

LOGIC SYMBOL

PIN

DESCRIPTION

A0 - A18

Address Inputs

DQ0 - DQ7 Data Inputs/Outputs

CE\

Chip Enable

OE\

Output Enable

WE\

Write Enable

+5V Single Power Supply

Device Ground