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USB2504 数据表(PDF) 20 Page - Microchip Technology |
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USB2504 数据表(HTML) 20 Page - Microchip Technology |
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20 / 42 page ![]() USB2504/USB2504A DS000002250A-page 20 2007 - 2016 Microchip Technology Inc. 5.3.1.1 Byte Protocols When using the Hub SMBus Interface for byte transfers, a write will always consist of the SMBus Interface Slave Address byte, followed by the Internal Address Register byte, then the data byte. The normal read protocol consists of a write to the HUB with the SMBus Interface Address byte, followed by the Internal Address Register byte. Then restart the Serial Communication with a Read consisting of the SMBus Interface Address byte, followed by the data byte read from the Hub. This can be accomplished by using the Read Byte protocol. Write Byte The Write Byte protocol is used to write data to the registers. The data will only be written if the protocol shown in Table 5-2 is performed correctly. Only one byte is transferred at a time for a Write Byte protocol. Read Byte The Read Byte protocol is used to read data from the registers. The data will only be read if the protocol shown in Table 5-3 is performed correctly. Only one byte is transferred at a time for a Read Byte protocol. 5.3.2 INVALID PROTOCOL RESPONSE BEHAVIOR Registers that are accessed with an invalid protocol are not updated. A register is only updated following a valid protocol. The only valid protocols are Write Byte and Read Byte, which are described above. The Hub only responds to the hardware selected Slave Address. Attempting to communicate with the Hub over SMBus with an invalid slave address or invalid protocol results in no response, and the SMBus Slave Interface returns to the idle state. The only valid registers that are accessible by the SMBus slave address are the registers defined in the Registers Sec- tion. See Section 5.3.3 for the response to undefined registers. 5.3.3 GENERAL CALL ADDRESS RESPONSE The Hub does not respond to a general call address of 0000_000b. 5.3.4 SLAVE DEVICE TIME-OUT According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than 35ms (TTIMEOUT, MAX). Note: Data bytes are transferred MSB first (msb first). Note: For the following SMBus tables: TABLE 5-2: SMBUS WRITE BYTE PROTOCOL Field: Start Slave Addr Wr Ack Reg. Addr Ack Reg. Data Ack Stop Bits: 1 71 18 1 8 1 1 TABLE 5-3: SMBUS READ BYTE PROTOCOL Field: Start Slave Addr Wr Ack Reg. Addr Ack Start Slave Addr Rd Ack Reg. Data Nack Stop Bits: 1 7 1 1 8 1 1 7 1 1 8 1 1 Denotes Master-to-Slave Denotes Slave-to-Master |
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