STM32F413RHT6 datasheet(130/207 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F413xG/H

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6.3.19

Communications interfaces

I2C interface characteristics

The I2C interface meets the requirements of the standard I2C communication protocol with

the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-

drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is

disabled, but is still present.

The I2C characteristics are described in Table 63. Refer also to Section 6.3.16: I/O port

characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

The I2C bus interface supports standard mode (up to 100 kHz) and fast mode (up to 400

kHz). The I2C bus frequency can be increased up to 1 MHz. For more details about the

complete solution, contact your local ST sales representative.

Table 63. I2C characteristics

Symbol

Parameter

Standard mode I2C(1)(2)

Fast mode I2C(1)(2)

Unit

Min

Max

Min

Max

tw(SCLL)

SCL clock low time

4.70

1.30

µs

tw(SCLH)

SCL clock high time

4.0

0.60

tsu(SDA)

SDA setup time

0.25

0.10

th(SDA)

SDA data hold time

tv(SDA,ACK) SDA data hold time

3.45(3)

-0.90(4)

tr(SDA)

tr(SCL)

SDA and SCL rise time

0.100

0.30

tf(SDA)

tf(SCL)

SDA and SCL fall time

0.30

th(STA)

Start condition hold time

0.6

tsu(STA)

Repeated Start condition setup

time

4.7

0.6

tsu(STO)

Stop condition setup time

0.60

tw(STO:STA)

Stop to Start condition time (bus

free)

4.70

1.3

tSP

Pulse width of the spikes that are

suppressed by the analog filter

for standard fast mode

0.05

0.10(5)

Capacitive load for each bus line

400

1. Guaranteed by design.

2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve fast mode

I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode clock.

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region

of the falling edge of SCL.

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

5. The minimum width of the spikes filtered by the analog filter is above tSP (max)

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