ADE7754AR datasheet(9/44 Pages) AD

9 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 9 –

Pin No.

MNEMONIC

DESCRIPTION

CLKIN

Master clock for ADCs and digital signal processing. An external clock can be pro-

vided at this logic input. Alternatively, a parallel resonant AT crystal can be connected

across CLKIN and CLKOUT to provide a clock source for the ADE7754. The clock

frequency for specified operation is 10MHz. Ceramic load capacitors of between 22pF

and 33pF should be used with the gate oscillator circuit. Refer to crystal manufacturers

data sheet for load capacitance requirements

CLKOUT

A crystal can be connected across this pin and CLKIN as described above to provide a

clock source for the ADE7754. The CLKOUT pin can drive one CMOS load when

either an external clock is supplied at CLKIN or a crystal is being used.

Chip Select. Part of the four wire Serial Interface. This active low logic input allows

the ADE7754 to share the serial bus with several other devices. See ADE7754 Serial Inter-

face.

D I N

Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of

SCLK—see ADE7754 Serial Interface.

SCLK

Serial Clock Input for the synchronous serial interface. All Serial data transfers are

synchronized to this clock—see ADE7754 Serial Interface. The SCLK has a Schmidt-trig-

ger Input for use with a clock source which has a slow edge transition time, e.g.,

opto-isolator outputs etc.

DOUT

Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of

SCLK. This logic output is normally in a high impedance state unless it is driving data

onto the serial data bus—see ADE7754 Serial Interface.

PIN CONFIGURATION

SOIC Package

TOP VIEW

(Not to Scale)

ADE7754

REFIn/Out

AGND

ICN

ICP

IBN

DGND

DVDD

AVDD

IBP

IAN

IAP

VCP

VBP

VAP

RESET

SCLK

DIN

DOUT

IRQ

CLKIN

CLKOUT

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