ADE7754AR datasheet(29/44 Pages) AD

29 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 29 –

Figure 36 shows this Apparent Energy accumulation for full

scale signals (sinusoidal) on the analog inputs. The three

curves displayed, illustrate the minimum time it takes the

energy register to roll-over when the individual VA Gain

registers contents are all equal to 3FFh, 000h and 800h. The

VA Gain registers are used to carry out an apparent power

calibration in the ADE7754. As shown, the fastest integration

time will occur when the VA Gain registers are set to

maximum full scale, i.e., 3FFh.

00,0000h

7F,FFFFh

80,0000h

3F,FFFFh

40,0000h

VAENERGY[23:0]

Time

(seconds)

AVAG = BVAG = CVAG = 3FFh

131

262

393

65.5

196.5

327.5

AVAG = BVAG = CVAG = 000h

AVAG = BVAG = CVAG = 800h

Figure 36 - Energy register roll-over time for full-scale

power (Minimum & Maximum Power Gain)

Note that the Apparent Energy register contents roll-over to

full-scale negative (80,0000h) and continue increasing in

value when the power or energy flow is positive - see Figure

36.

By using the Interrupt Enable register, the ADE7754 can be

configured to issue an interrupt (IRQ) when the Apparent

Energy register is half full (positive or negative).

Integration times under steady load

As mentioned in the last section, the discrete time sample

period (T) for the accumulation register is 1.2µs (12/

CLKIN). With full-scale sinusoidal signals on the analog

inputs and the VA Gain registers set to 000h, the average

word value from each Apparent Power stage is D1B71h - see

Apparent Power output range. The maximum value which can be

stored in the Apparent Energy register before it over-flows is

23 -1or FF,FFFFh. As the average word value is added to

the

internal

which

can

store

FFFF,FFFF,FFFFh before it overflows, the integration

time under these conditions with VADIV=0 is calculated as

follows:

Time

FFFF FFFF FFFFh

×=

.min

31 71

1 2

131

When VADIV is set to a value different from 0, the integra-

tion time varies as shown on Equation 23.

Time = TimeWDIV=0 x VADIV

(23)

LINE APPARENT ENERGY ACCUMULATION

The ADE7754 is designed with a special Apparent Energy

accumulation mode which simplifies the calibration process.

By using the on-chip zero-crossing detection, the ADE7754

accumulates the Apparent Power signal in the LVAENERGY

Figure 37. The line Apparent energy accumulation mode is

always active.

Each one of three phases zero-crossing detection can contrib-

ute to the accumulation of the half line cycles. Phase A, B and

C zero crossings are taken into account when counting the

number of half line cycle by setting to logic one bits 4-6 of

the MMODE register. Selecting phases for the Zero crossing

counting has also the effect of enabling the Zero-crossing

detection, Zero-crossing Time-Out and Period Measure-

ment for the corresponding phase as described in the

Zero-crossing Detection paragraph.

The number of half line cycles is specified in the LINCYC

ADE7754 can accumulate Apparent Power for up to 65535

combined half cycles. Because the Apparent Power is inte-

grated on the same integral number of line cycles as the Line

Active Energy register, these two values can be compared

easily - see Energy Scaling. The active and

apparent Energy

are calculated more accurately because of this precise timing

control and provide all the information needed for Reactive

Power and Power Factor calculation. At the end of an energy

calibration cycle the LINCYC flag in the Interrupt Status

Thus the IRQ line can also be used to signal the end of a

calibration.

CALIBRATION

CONTROL

LINCYC[15:0]

Apparent Power

Phase A

Apparent Power

Phase B

Apparent Power

Phase C

ACCUMULATE APPARENT POWER DURING

LINCYC ZERO-CROSSINGS

LVAENERGY[23:0]

VADIV

LPF1

FROM VA

ADC

ZEROCROSS

DETECT

LPF1

FROM VB

ADC

ZEROCROSS

DETECT

LPF1

FROM VC

ADC

ZEROCROSS

DETECT

MMODE register

bit 6

MMODE register

bit 4

MMODE register

bit 5

Figure 37 - ADE7754 Apparent Energy Calibration

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