ADE7754AR datasheet(12/44 Pages) AD

12 / 44 page

REV. PrG 01/03

PRELIMINARY TECHNICAL DATA

ADE7754

– 12 –

CURRENT CHANNEL ADC

Figure 8 shows the ADC and signal processing chain for the

input IA of the current channels (same for IB and IC). In

waveform sampling mode the ADC outputs are signed 2’s

Complement 24-bit data word at a maximum of 26.0kSPS

(kilo Samples Per Second). The output of the ADC can be

scaled by ±50% by using the APGAINs register. While the

ADC outputs are 24-bit 2's complement value the maximum

full-scale positive value from the ADC is limited to 400000h

(+4,194,304d). The maximum full-scale negative value is

limited to C00000h (-4,194,304d). If the analog inputs are

over-ranged, the ADC output code clamps at these values.

With the specified full scale analog input signal of ±0.5V, the

ADC produces an output code between D70A3Eh (-

2,684,354) and 28F5C2h (+2,684,354). This is illustrated

in Figure 8. The diagram in Figure 8 shows a full-scale

voltage signal being applied to the differential inputs IAP and

IAN.

Current channel ADC Gain Adjust

The ADC gain in each phase of the Current Channel can be

adjusted by using the multiplier and Active Power Gain

The gain of the ADC is adjusted by writing a 2’s complement

12-bit word to the Active Power Gain register. Below is the

expression that shows how the gain adjustment is related to

the contents of the Active Power Gain register.

Code

ADC

AAPGAIN

=×





















For example when 7FFh is written to the Active Power Gain

2047/2

12 = 0.5. Similarly, 800h = -2047 Dec (signed 2’s

Complement) and ADC output is scaled by –50%. These two

examples are illustrated graphically in Figure 8.

Current channel Sampling

The waveform samples of the current channel

inputs may

also be routed to the WAVEFORM register (WAVMODE

system master (MCU). The Active Energy and Apparent

Energy calculation will remain uninterrupted during wave-

form sampling.

When in waveform sample mode, one of four output sample

rates may be chosen by using bits 3 and 4 of the WAVMode

may be 26.0kSPS, 13.0kSPS, 6.5kSPS or 3.3kSPS—see

WAVMode register. By setting the WSMP bit in the Interrupt

Mask register to logic one, the interrupt request output IRQ

will go active low when a sample is available. The timing is

shown in Figure 9. The 24-bit waveform samples are trans-

ferred from the ADE7754 one byte (8-bits) at a time, with the

most significant byte shifted out first.

0 0

09 Hex

IRQ

DIN

DOUT

SCLK

Read from WAVEFORM

Current channel DATA - 24 bits

SGN

Figure 9 – Waveform sampling current channel

The interrupt request output IRQ stays low until the interrupt

routine reads the Reset Status register - see ADE7754 Inter-

rupt.

Note: If the WSMP bit in the interrupt MASK register is not

set to logic one, no data is available in the Waveform register.

HPF

IAP

IAN

ADC

PGA1

800Hex - 7FFHex

REFERENCE

AAPGAIN[11:0]

Vin

000000h

400000h

C00000h

28F5C2h

D70A3Eh

+ 100% FS

- 100% FS

00000h

28F5C2h

+ 100% FS

- 100% FS

D70A3Eh

+ 150% FS

+ 50% FS

- 50% FS

- 150% FS

3D70A3h

147AE1h

EB851Fh

C28F5Dh

AAPGAIN[11:0]

000h 7FFh

800h

Analog

Input

Range

ADC Output

word Range

Channel 1

ACTIVE AND REACTIVE

POWER CALCULATION

WAVEFORM SAMPLE

Sinc3

MULTIPLIER

Digital LPF

x1, x2, x4

GAIN[1:0]

0.5 V / GAIN1

CURRENT RMS

CALCULATION

100% FS

Figure 8 - ADC and signal processing in current channel

ADE7754AR 数据表(PDF) 12 Page - Analog Devices

ADE7754AR 数据表(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载