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TUSB2136 数据表(PDF) 17 Page - Texas Instruments

部件名 TUSB2136
功能描述  UNIVERSAL SERIAL BUS KEYBOARD HUB CONTROLLER
PDF  50 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TUSB2136 数据表(HTML) 17 Page - Texas Instruments

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2–5
Table 2–2. Memory-Mapped Registers Summary (XDATA Range = FF80
→ FFFF)
ADDRESS
REGISTER
DESCRIPTION
FFFF
FUNADR
FUNADR: Function address register
FFFE
USBSTA
USBSTA: USB status register
FFFD
USBMSK
USBMSK: USB interrupt mask register
FFFC
USBCTL
USBCTL: USB control register
FFFB
HUBVIDH
HUBVIDH: HUB-VID register (high-byte)
FFFA
HUBVIDL
HUBVIDL: HUB-VID register (low-byte)
FFF9
HUBPIDH
HUBPIDH: HUB-PID register (high-byte)
FFF8
HUBPIDL
HUBPIDL: HUB-PID register (low-byte)
FFF7
HUBCNFG
HUBCNFG: HUB-configuration register
FFF6
VIDSTA
VIDSTA: VID/PID status register
FFF5
HUBPOTG
HUBPOTG: HUB power-on to power-good descriptor register
FFF4
HUBCURT
HUBCURT: HUB current descriptor register
FFF3
I2CADR
I2CADR: I2C address register
FFF2
I2CDAI
I2CDAI: I2C data-input register
FFF1
I2CDAO
I2CDAO: I2C data-output register
FFF0
I2CSTA
I2CSTA: I2C status and control register
RESERVED
FF97
PUR3
Port 3 pullup resistor register
FF96
PUR2
Port 2 pullup resistor register
FF95
PUR1
Port 1 pullup resistor register
FF94
PUR0
Port 0 pullup resistor register
FF93
WDCSR
WDCSR: Watchdog timer, control and status register
FF92
VECINT
VECINT: Vector interrupt register
FF91
RESERVED
FF90
MCNFG
MCNFG: MCU configuration register
RESERVED
FF84
INTCFG
INTCFG: Interrupt delay configuration register
FF83
OEPBCNT_0
OEPBCNT_0: Output endpoint-0 byte count register
FF82
OEPCNFG_0
OEPCNFG_0: Output endpoint-0 configuration register
FF81
IEPBCNT_0
IEPBCNT_0: Input endpoint-0 byte count register
FF80
IEPCNFG_0
IEPCNFG_0: Input endpoint-0 configuration register
2.4
Endpoint Descriptor Block (EDB-1 to EDB-3)
Data transfers between USB, MCU and external devices are defined by an endpoint descriptor block (EDB). Four
input and four output EDBs are provided. With the exception of EDB-0 (I/O endpoint 0), all EDBs are located in SRAM
as shown in Table 2–3. Each EDB contains information describing the X and Y buffers. In addition, it provides general
status information.



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